A Method to Characterize n[sup +]-Polysilicon/Oxide Interface Traps in Ultrathin Oxides

2001 ◽  
Vol 4 (6) ◽  
pp. G47 ◽  
Author(s):  
Kow Ming Chang ◽  
Yuan Hung Chung ◽  
Tzyk Cheang Lee ◽  
Yong Long Sun
Keyword(s):  
Interface Traps ◽  
Oxide Interface ◽  
Ultrathin Oxides

2D MoS 2 Charge Injection Memory Transistors Utilizing Hetero‐Stack SiO 2 /HfO 2 Dielectrics and Oxide Interface Traps

2021 ◽  
pp. 2100074
Author(s):  
Livia Janice Widiapradja ◽  
Taewook Nam ◽  
Yeonsu Jeong ◽  
Hye‐Jin Jin ◽  
Yangjin Lee ◽  
...  
Keyword(s):  
Charge Injection ◽  
Interface Traps ◽  
Oxide Interface

Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices

1996 ◽  
Vol 43 (7) ◽  
pp. 1144-1152 ◽  
Author(s):  
H.-H. Vuong ◽  
C.S. Rafferty ◽  
S.A. Eshraghi ◽  
J.L. Lentz ◽  
P.M. Zeitzoff ◽  
...  
Keyword(s):  
Process Modeling ◽  
Interface Traps ◽  
Oxide Interface ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion

From planar to vertical nanowires field-effect transistors

2012 ◽  
Vol 1439 ◽  
pp. 101-107
Author(s):  
Guillaume Rosaz ◽  
Bassem Salem ◽  
Nicolas Pauc ◽  
Pascal Gentile ◽  
Priyanka Periwal ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
The State ◽  
Hysteretic Behavior ◽  
Interface Trap ◽  
Interface Traps ◽  
Oxide Interface ◽  
Back Gate ◽  
Technological Processes

ABSTRACTThe authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

scholarly journals Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors

2015 ◽  
Vol 2015 ◽  
pp. 1-14
Author(s):  
Zhi Jiang ◽  
Yiqi Zhuang ◽  
Cong Li ◽  
Ping Wang ◽  
Yuqi Liu
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Great Influence ◽  
Peak Shift ◽  
Flat Band ◽  
Interface Traps ◽  
Oxide Interface ◽  
Band Shift ◽  
Simulation Tools ◽  
The Impact

We demonstrate the impact of semiconductor/oxide interface traps (ITs) on the DC and AC characteristics of tunnel field-effect transistors (TFETs). Using the Sentaurus simulation tools, we show the impacts of trap density distribution and trap type on the n-type double gate- (DG-) TFET. The results show that the donor-type and acceptor-type ITs have the great influence on DC characteristic at midgap. Donor-like and acceptor-like ITs have different mechanism of the turn-on characteristics. The flat band shift changes obviously and differently in the AC analysis, which results in contrast of peak shift of Miller capacitorCgdfor n-type TFETs with donor-like and acceptor-like ITs.

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