scholarly journals Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors

2015 ◽  
Vol 2015 ◽  
pp. 1-14
Author(s):  
Zhi Jiang ◽  
Yiqi Zhuang ◽  
Cong Li ◽  
Ping Wang ◽  
Yuqi Liu
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Great Influence ◽  
Peak Shift ◽  
Flat Band ◽  
Interface Traps ◽  
Oxide Interface ◽  
Band Shift ◽  
Simulation Tools ◽  
The Impact

We demonstrate the impact of semiconductor/oxide interface traps (ITs) on the DC and AC characteristics of tunnel field-effect transistors (TFETs). Using the Sentaurus simulation tools, we show the impacts of trap density distribution and trap type on the n-type double gate- (DG-) TFET. The results show that the donor-type and acceptor-type ITs have the great influence on DC characteristic at midgap. Donor-like and acceptor-like ITs have different mechanism of the turn-on characteristics. The flat band shift changes obviously and differently in the AC analysis, which results in contrast of peak shift of Miller capacitorCgdfor n-type TFETs with donor-like and acceptor-like ITs.

From planar to vertical nanowires field-effect transistors

2012 ◽  
Vol 1439 ◽  
pp. 101-107
Author(s):  
Guillaume Rosaz ◽  
Bassem Salem ◽  
Nicolas Pauc ◽  
Pascal Gentile ◽  
Priyanka Periwal ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
The State ◽  
Hysteretic Behavior ◽  
Interface Trap ◽  
Interface Traps ◽  
Oxide Interface ◽  
Back Gate ◽  
Technological Processes

ABSTRACTThe authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

Low Frequency Noise Analysis of Monolithically Fabricated 4H-SiC CMOS Field Effect Transistors

2014 ◽  
Vol 778-780 ◽  
pp. 428-431 ◽  
Author(s):  
Lucy Claire Martin ◽  
Hua Khee Chan ◽  
David T. Clark ◽  
Ewan P. Ramsay ◽  
A.E. Murphy ◽  
...  
Keyword(s):  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Noise Analysis ◽  
Low Frequency ◽  
Frequency Noise ◽  
Interface Traps ◽  
Low Frequency Noise ◽  
Noise Characteristics ◽  
The Impact

Low frequency noise in 4H-SiC lateral p-channel metal oxide semiconductor field effect transistors (PMOSFETs) in the frequency range from 1 Hz to 100 kHz has been used to investigate the relationship between gate dielectric fabrication techniques and the resulting density of interface traps at the semiconductor-dielectric interface in order to examine the impact on device performance. The results show that the low frequency noise characteristics in p-channel 4H-SiC MOSFETs in weak inversion are in agreement with the McWhorter model and are dominated by the interaction of channel carriers with interface traps at the gate dielectric/semiconductor interface.

scholarly journals Numerical Evaluation of the Effect of Geometric Tolerances on the High-Frequency Performance of Graphene Field-Effect Transistors

Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 3121
Author(s):  
Monica La Mura ◽  
Patrizia Lamberti ◽  
Vincenzo Tucci
Keyword(s):  
High Frequency ◽  
Communication Systems ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Geometrical Parameters ◽  
Effect Transistor ◽  
Rf Performance ◽  
The Impact

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.

Insight into Channel Conduction Mechanisms of 4H-SiC(0001) MOSFET Based on Temperature-Dependent Hall Effect Measurement

2020 ◽  
Vol 1004 ◽  
pp. 620-626
Author(s):  
Hironori Takeda ◽  
Mitsuru Sometani ◽  
Takuji Hosoi ◽  
Takayoshi Shimura ◽  
Hiroshi Yano ◽  
...  
Keyword(s):  
Hall Effect ◽  
Field Effect ◽  
Elevated Temperatures ◽  
Field Effect Transistors ◽  
Free Carrier ◽  
Oxide Semiconductor ◽  
Thermal Excitation ◽  
Temperature Dependent ◽  
Conduction Mechanisms ◽  
The Impact

Temperature-dependent Hall effect measurements were conducted to investigate the channel conduction mechanisms of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). This method allows us to discriminate the impact of the density of mobile (free) carriers in the inversion channels and their net mobility on the performance of SiC MOSFETs. It was found that, while the free carrier ratio of SiC MOSFETs with conventional gate oxides formed by dry oxidation is below 4% at 300 K, increasing the free carrier ratio due to thermal excitation of trapped electrons from SiO2/SiC interfaces leads to an unusual improvement in the field-effect mobility of SiC MOSFETs at elevated temperatures. Specifically, a significant increase in free carrier density surpasses the mobility degradation caused by phonon scattering for thermally grown SiO2/SiC interfaces. It was also found that, although nitrogen incorporation in SiO2/SiC interfaces increases the free carrier ratio typically up to around 30%, introduction of an additional scattering factor associated with interface nitridation compensates for the moderate amount of thermally generated mobile carriers at high temperatures, indicating a fundamental drawback of nitridation of SiO2/SiC interfaces. On the basis of these findings, we discuss the channel conduction mechanisms of SiC MOSFETs.

A New Approach to the Characteristics and Short-Channel Effects of Double-Gate Carbon Nanotube Field-Effect Transistors using MATLAB: A Numerical Study

2012 ◽  
Vol 67 (6-7) ◽  
pp. 317-326 ◽  
Author(s):  
Alireza Heidari ◽  
Niloofar Heidari ◽  
Foad Khademi Jahromi ◽  
Roozbeh Amiri ◽  
Mohammadali Ghorbani
Keyword(s):  
Carbon Nanotube ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Open Boundary ◽  
Double Gate ◽  
Short Channel Effects ◽  
Drain Voltage ◽  
Short Channel ◽  
Channel Effects ◽  
The Impact

In this paper, first, the impact of different gate arrangements on the short-channel effects of carbon nanotube field-effect transistors with doped source and drain with the self-consistent solution of the three-dimensional Poisson equation and the Schr¨odinger equation with open boundary conditions, within the non-equilibrium Green function, is investigated. The results indicate that the double-gate structure possesses a quasi-ideal subthreshold oscillation and an acceptable decrease in the drain induced barrier even for a relatively thick gate oxide (5 nm). Afterward, the electrical characteristics of the double-gate carbon nanotube field-effect transistors (DG-CNTFET) are investigated. The results demonstrate that an increase in diameter and density of the nanotubes in the DG-CNTFET increases the on-state current. Also, as the drain voltage increases, the off-state current of the DG-CNTFET decreases. In addition, regarding the negative gate voltages, for a high drain voltage, increasing in the drain current due to band-to-band tunnelling requires a larger negative gate voltage, and for a low drain voltage, resonant states appear

scholarly journals Quantum Treatment of Inelastic Interactions for the Modeling of Nanowire Field-Effect Transistors

Materials ◽  
2019 ◽  
Vol 13 (1) ◽  
pp. 60 ◽  
Author(s):  
Youseung Lee ◽  
Demetrio Logoteta ◽  
Nicolas Cavassilas ◽  
Michel Lannoo ◽  
Mathieu Luisier ◽  
...  
Keyword(s):  
Inelastic Scattering ◽  
Field Effect ◽  
Phonon Scattering ◽  
Field Effect Transistors ◽  
Order Approximation ◽  
Three Dimensional ◽  
Computational Time ◽  
Thermal Current ◽  
The Impact ◽  
Quantum Treatment

During the last decades, the Nonequilibrium Green’s function (NEGF) formalism has been proposed to develop nano-scaled device-simulation tools since it is especially convenient to deal with open device systems on a quantum-mechanical base and allows the treatment of inelastic scattering. In particular, it is able to account for inelastic effects on the electronic and thermal current, originating from the interactions of electron–phonon and phonon–phonon, respectively. However, the treatment of inelastic mechanisms within the NEGF framework usually relies on a numerically expensive scheme, implementing the self-consistent Born approximation (SCBA). In this article, we review an alternative approach, the so-called Lowest Order Approximation (LOA), which is realized by a rescaling technique and coupled with Padé approximants, to efficiently model inelastic scattering in nanostructures. Its main advantage is to provide a numerically efficient and physically meaningful quantum treatment of scattering processes. This approach is successfully applied to the three-dimensional (3D) atomistic quantum transport OMEN code to study the impact of electron–phonon and anharmonic phonon–phonon scattering in nanowire field-effect transistors. A reduction of the computational time by about ×6 for the electronic current and ×2 for the thermal current calculation is obtained. We also review the possibility to apply the first-order Richardson extrapolation to the Padé N/N − 1 sequence in order to accelerate the convergence of divergent LOA series. More in general, the reviewed approach shows the potentiality to significantly and systematically lighten the computational burden associated to the atomistic quantum simulations of dissipative transport in realistic 3D systems.

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