Influence of Oxide Breakdown Percolation Resistance on MOSFETs (Invited Paper)

2019 ◽  
Vol 6 (3) ◽  
pp. 431-447
Author(s):  
Kin Leong Pey ◽  
Vui Lip Lo ◽  
Chih Hang Tung ◽  
Wai Tat Lim ◽  
Diing Shenp Ang
Keyword(s):  
Oxide Breakdown

A Study of Pad Contamination Defect and Removal

2008 ◽  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Oxide ◽  
Action Plans ◽  
Preventive Action ◽  
Oxide Breakdown ◽  
Reliability Level ◽  
The Future ◽  
Dry Etch ◽  
Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Fundamental Considerations for CDM Failure in 90nm Products

2006 ◽  
Author(s):  
Nobuyuki Wakai ◽  
Yuji Kobira ◽  
Hidemitsu Egawa ◽  
Masayoshi Tsutsumi
Keyword(s):  
Breakdown Voltage ◽  
High Speed ◽  
Gate Oxide ◽  
Critical Parameters ◽  
Protection Device ◽  
Oxide Breakdown ◽  
Technology Products ◽  
Charged Device ◽  
Device Size ◽  
Fundamental Consideration

Abstract Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.

Effect of SC1 Process on Silicon Surface Microroughness and Oxide Breakdown Characteristics

1995 ◽  
Vol 34 (Part 2, No. 2A) ◽  
pp. L153-L155 ◽  
Author(s):  
Kazuhiro Akiyama ◽  
Nobumasa Naito ◽  
Motoaki Nagamori ◽  
Hiroshi Koya ◽  
EtsuroMorita ◽  
...  
Keyword(s):  
Silicon Surface ◽  
Oxide Breakdown ◽  
Surface Microroughness

Ring oscillator behavior after oxide breakdown

2005 ◽  
Author(s):  
R. Fernandez ◽  
R. Rodriguez ◽  
M. Nafria ◽  
X. Aymerich
Keyword(s):  
Ring Oscillator ◽  
Oxide Breakdown
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