Anomalous Field Transistor BTI Failure Mechanism in an 80V Technology

Abstract An investigation into latent CMOS device isolation failures during the process development phase of an advanced 0.35 μm CMOS ASIC process is presented. The failure mechanism manifested itself electrically during wafer sort as a non-typical Iddq distribution and subsequently resulted in large leakage failures during reliability stress testing experiments. Emission microscopy analysis on failing units revealed specific leakage sites in the CMOS SRAM core. Layer removal/SEM inspections revealed no physical anomalies in the emission area. Manual toggling of the RAM internal electrical nodes revealed that the leakage occurred through a parasitic field transistor (i.e. between two P+ diffusion islands gated by a polysilicon runner). Probing of test structures with similar layout features revealed that the diffusion isolation between the P+ diffusions was marginal, resulting in subthreshold field leakage. In addition, the subthreshold leakage current between the two diffusions on the test structures increased as a function of stress voltage and time - similar to the failing signature of the actual SRAM. The mechanism responsible for the latent increase in leakage current is believed to be electron trapping near the drain end of the parasitic field device. Improvement of the transistor isolation properties was achieved through process modifications and subsequently the failure mechanism was eliminated

On the role of tin underlays for the prevention of thermal grooving in thin gold films

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100145030 ◽

1986 ◽

Vol 44 ◽

pp. 732-733

Author(s):

Jin Young Kim ◽

R. E. Hummel ◽

R. T. DeHoff

Keyword(s):

Thin Film ◽

Free Surface ◽

Grain Boundary ◽

Beneficial Effect ◽

Failure Mechanism ◽

Failure Mechanisms ◽

Distinct Advantage ◽

Gold Films ◽

Gold Thin Film

Gold thin film metallizations in microelectronic circuits have a distinct advantage over those consisting of aluminum because they are less susceptible to electromigration. When electromigration is no longer the principal failure mechanism, other failure mechanisms caused by d.c. stressing might become important. In gold thin-film metallizations, grain boundary grooving is the principal failure mechanism.Previous studies have shown that grain boundary grooving in gold films can be prevented by an indium underlay between the substrate and gold. The beneficial effect of the In/Au composite film is mainly due to roughening of the surface of the gold films, redistribution of indium on the gold films and formation of In2O3 on the free surface and along the grain boundaries of the gold films during air annealing.

ICE FIELD TRANSISTOR

Le Journal de Physique Colloques ◽

10.1051/jphyscol:1987117 ◽

1987 ◽

Vol 48 (C1) ◽

pp. C1-115-C1-119 ◽

Cited By ~ 7

Author(s):

V. F. PETRENKO ◽

N. MAENO

Keyword(s):

Ice Field ◽

Field Transistor

Influence of Air Entrappment on Flood Embankment Failure Mechanism - Model Tests

Technical Sciences ◽

10.2478/v10022-008-0015-y ◽

2008 ◽

Vol 11 (-1) ◽

pp. 188-201 ◽

Cited By ~ 2

Author(s):

Piotr Bogacz ◽

Jarosława Kaczmarek ◽

Danuta Leśniewska

Keyword(s):

Failure Mechanism ◽

Model Tests ◽

Mechanism Model

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0191 ◽

2010 ◽

Author(s):

William Ng ◽

Kevin Weaver ◽

Zachary Gemmill ◽

Herve Deslandes ◽

Rudolf Schlangen

Keyword(s):

Failure Mechanism ◽

Integrated Circuit ◽

Printed Circuit Board ◽

Hot Spot ◽

Circuit Board ◽

Discrete Component ◽

Printed Circuit ◽

Thermal Signature ◽

Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0049 ◽

2010 ◽

Author(s):

Sarven Ipek ◽

David Grosjean

Keyword(s):

Failure Analysis ◽

Failure Mechanism ◽

Photon Emission ◽

Fault Isolation ◽

Yield Enhancement ◽

Analysis Technique ◽

Laser Signal ◽

Signal Injection ◽

Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Unique Autoclave Stress Induced Failure Mechanism

ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2005p0427 ◽

2005 ◽

Author(s):

John Butchko ◽

Bruce T. Gillette

Keyword(s):

Corrosion Rate ◽

Grain Boundary ◽

Failure Analysis ◽

Failure Mechanism ◽

Metal Corrosion ◽

Corrosion Mechanism ◽

Reliability Testing ◽

Process Change ◽

Transistor Reliability ◽

Pass Through

Abstract Autoclave Stress failures were encountered at the 96 hour read during transistor reliability testing. A unique metal corrosion mechanism was found during the failure analysis, which was creating a contamination path to the drain source junction, resulting in high Idss and Igss leakage. The Al(Si) top metal was oxidizing along the grain boundaries at a faster rate than at the surface. There was subsurface blistering of the Al(Si), along with the grain boundary corrosion. This blistering was creating a contamination path from the package to the Si surface. Several variations in the metal stack were evaluated to better understand the cause of the failures and to provide a process solution. The prevention of intergranular metal corrosion and subsurface blistering during autoclave testing required a materials change from Al(Si) to Al(Si)(Cu). This change resulted in a reduced corrosion rate and consequently prevented Si contamination due to blistering. The process change resulted in a successful pass through the autoclave testing.

The Use of TMAH to Etch Silicon and Expose Metal Bridging Failures

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0231 ◽

2000 ◽

Author(s):

Mark Morris ◽

James Mohr ◽

Esteban Ortiz ◽

Steven Englebretson

Keyword(s):

Failure Mechanism ◽

Schottky Diodes ◽

Tetramethylammonium Hydroxide ◽

Novel Approach ◽

Failure Location ◽

Metal Etching ◽

Plastic Mold

Abstract Determination of metal bridging failures on plastic encapsulated devices is difficult due to the metal etching effects that occur while removing many of the plastic mold compounds. Typically, the acids used to remove the encapsulation are corrosive to the metals that are found within the device. Thus, decapsulation can result in removal of the failure mechanism. Mechanical techniques are often not successful due to damage that results in destruction of the die and failure mechanism. This paper discusses a novel approach to these types of failures using a silicon etch and a backside evaluation. The desirable characteristics of the technique would be to remove the silicon and leave typical device metals unaffected. It would also be preferable that the device passivation and oxides not be etched so that the failure location is not disturbed. The use of Tetramethylammonium Hydroxide (TMAH), was found to fit these prerequisites. The technique was tested on clip attached Schottky diodes that exhibited resistive shorting. The use of the TMAH technique was successful at exposing thin solder bridges that extruded over the edge of the die resulting in failure.

Electromigration and Electrochemical Reaction Mixed Failure Mechanism in Gold Interconnection System

ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1999p0399 ◽

1999 ◽

Author(s):

Hide Murayama ◽

Makoto Yamazaki ◽

Shigeru Nakajima

Keyword(s):

Failure Mechanism ◽

Failure Rate ◽

Electrochemical Reaction ◽

Dielectric Films ◽

Failure Rates ◽

Interlayer Dielectric ◽

Bipolar Devices ◽

Gold Metallization

Abstract Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations are the same for the failed devices. From a statistical lot analysis, it is found that the short failure rate is higher for devices with thinner interlayer dielectric films. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.