Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique

Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.

On the Influence on the Operation of the Quadrated Transistor of Short Circuits between the Gate of a Single Transistor, its other Outputs and the Power Source

The influence on the operation of the quadrated transistor of short circuits between the gate of the field transistor and its other outputs (source, drain, substrate) and also its power source with input signals 0 and 1 on the gate for two variants of the quadrated transistor circuit is considered. It is shown that in an overwhelming number of cases the result at the output of the quadrated transistor is correct.

FEATURES OF KEY PARAMETERS OF FIELD TRANSISTORS

In this paper, the dependence of stock current on the channel closing voltage in the main parameters of the field transistor (stock), dynamic resistance and channel closing mode has been investigated. The optimal values of the channel thickness are determined depending on the thickness of the p+-n junction volume charge region of the gate and the concentration of carriers that provide high sensitivity.