Analysis of a Latent Deep Submicron CMOS Device Isolation Leakage Mechanism

An investigation into latent CMOS device isolation failures during the process development phase of an advanced 0.35 μm CMOS ASIC process is presented. The failure mechanism manifested itself electrically during wafer sort as a non-typical Iddq distribution and subsequently resulted in large leakage failures during reliability stress testing experiments. Emission microscopy analysis on failing units revealed specific leakage sites in the CMOS SRAM core. Layer removal/SEM inspections revealed no physical anomalies in the emission area. Manual toggling of the RAM internal electrical nodes revealed that the leakage occurred through a parasitic field transistor (i.e. between two P+ diffusion islands gated by a polysilicon runner). Probing of test structures with similar layout features revealed that the diffusion isolation between the P+ diffusions was marginal, resulting in subthreshold field leakage. In addition, the subthreshold leakage current between the two diffusions on the test structures increased as a function of stress voltage and time - similar to the failing signature of the actual SRAM. The mechanism responsible for the latent increase in leakage current is believed to be electron trapping near the drain end of the parasitic field device. Improvement of the transistor isolation properties was achieved through process modifications and subsequently the failure mechanism was eliminated