Equivalent Oxide Thickness Reduction for High-k Gate Stacks by Optimized Rare-Earth Silicate Reactions

2009 ◽  
Vol 12 (5) ◽  
pp. G17 ◽  
Author(s):  
S. Van Elshocht ◽  
C. Adelmann ◽  
P. Lehnen ◽  
S. De Gendt
Keyword(s):  
Rare Earth ◽  
Oxide Thickness ◽  
Thickness Reduction ◽  
Equivalent Oxide Thickness ◽  
Gate Stacks ◽  
High K

Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

2004 ◽  
Vol 811 ◽  
Author(s):  
Joel Barnett ◽  
N. Moumen ◽  
J. Gutt ◽  
M. Gardner ◽  
C. Huffman ◽  
...  
Keyword(s):  
Experimental Study ◽  
Surface Preparation ◽  
Oxide Thickness ◽  
Electrical Performance ◽  
Electrical Characteristics ◽  
Equivalent Oxide Thickness ◽  
Gate Stacks ◽  
Thermal Oxide ◽  
High K ◽  
Preparation Techniques

ABSTRACTWe have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

Electrical Properties in High-k HfO[sub 2] Capacitors with an Equivalent Oxide Thickness of 9 Å on Ru Metal Electrode

2005 ◽  
Vol 8 (6) ◽  
pp. F17 ◽  
Author(s):  
Jeon-Ho Kim ◽  
Soon-Gil Yoon ◽  
Seung-Jin Yeom ◽  
Hyun-Kyung Woo ◽  
Deok-Sin Kil ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Metal Electrode ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
High K

Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness

Silicon ◽  
2019 ◽  
Vol 12 (7) ◽  
pp. 1567-1574
Author(s):  
Sanjit Kumar Swain ◽  
Satish Kumar Das ◽  
Sarosij Adak
Keyword(s):  
Oxide Thickness ◽  
Double Gate ◽  
Gate Stacks ◽  
High K ◽  
Double Gate Mosfet ◽  
Channel Gate

scholarly journals Microstructure and Electrical Properties of III-As Gate Stacks with Amorphous Rare-Earth High-k Oxides

2010 ◽  
Vol 16 (S2) ◽  
pp. 1412-1413
Author(s):  
S Oktyabrsky ◽  
R Kambhampati ◽  
V Tokranov ◽  
M Yakimov ◽  
T Heeg ◽  
...  
Keyword(s):  
Rare Earth ◽  
Electrical Properties ◽  
Gate Stacks ◽  
High K

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010.

The Effect of Ternary Material (Zr, Y, and O) High-k Gate Dielectrics

2013 ◽  
Vol 699 ◽  
pp. 422-425 ◽  
Author(s):  
K.C. Lin ◽  
C.H. Chou ◽  
J.Y. Chen ◽  
C.J. Li ◽  
J.Y. Huang ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Electrical Property ◽  
Leakage Current ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Gate Dielectrics ◽  
Bottom Layer ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
High K

In this research, the Y2O3 layer is doped with the zirconium through co-sputtering and rapid thermal annealing (RTA) at 550°C, 700°C, and 850°C. Then the Al electrode is deposited to generate two kinds of structures, Al/ZrN/ Y2O3/ Y2O3+Zr/p-Si and Al/ZrN/ Y2O3+Zr/ Y2O3/p-Si. According to the XRD results, when Zr was doped on the upper layer, the crystallization phenomenon was more significant than Zr was at the bottom layer, meaning that Zr may influence the diffusion of the oxygen. The AFM also shows that the surface roughness of Zr has worse performance. For the electrical property, the influence to overall leakage current is increased because the equivalent oxide thickness (EOT) is thinner.

Interface Engineering During Epitaxial Growth of High-K Lanthanide Oxides on Silicon

2006 ◽  
Vol 917 ◽  
Author(s):  
H. Joerg Osten ◽  
Malte Czernohorsky ◽  
Eberhard Bugiel ◽  
Dirk Kuehne ◽  
Andreas Fissel
Keyword(s):  
Molecular Beam ◽  
Oxygen Supply ◽  
Oxide Thickness ◽  
Interface Structure ◽  
Equivalent Oxide Thickness ◽  
Lanthanide Oxides ◽  
Partial Pressures ◽  
High K ◽  
Current Densities ◽  
Optimized Conditions

AbstractWe investigated the influence of additional oxygen supply and temperature during the growth of thin Gd2O3 layers on Si(001) with molecular beam epitaxy. Additional oxygen supply during growth improves the dielectric properties significantly; however too high oxygen partial pressures lead to an increase in the lower permittivity interfacial layer thickness. The growth temperature mainly influences the dielectric gate stack properties due to changes of the Gd2O3/Si interface structure. Optimized conditions (600 °C, pO2 = 5·10-7 mbar) were found to achieve equivalent oxide thickness values below 1 nm accompanied by leakage current densities below 1 mA/cm2 at 1 V.

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