scholarly journals Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-6 ◽  
Author(s):  
Ler Chun Lee ◽  
Abu Khari bin A'ain ◽  
Albert Victor Kordesch
Keyword(s):  
Noise Figure ◽  
Notch Filter ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Active Inductor ◽  
Cmos Process ◽  
Image Rejection ◽  
Fully Integrated ◽  
Active Inductors ◽  
Noise Amplifier

A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA) has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA). A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

An ESD Protected Wideband CMOS Low Noise Amplifier Employing Active Feedback Technique

2011 ◽  
Vol 403-408 ◽  
pp. 2809-2813
Author(s):  
Kuan Bao ◽  
Xiang Ning Fan
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Fully Integrated ◽  
Input Matching ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
On Chip

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic and input matching are simultaneously achieved by active-feedback technique. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Implemented in 0.18-μm CMOS process, the core size of the fully integrated LNA circuits is 535 μm×425 μm without any passive on-chip inductor. The simulated gain and the minimal noise figure of the CMOS LNA are 17.5 dB and 2.0 dB, respectively. The LNA achieves a -3dB bandwidth of 3.1 GHz. And the simulated IIP3 is -4.4 dBm at 2.5 GHz. Operating at 1.8V, the LNA draws a current of 7.7 mA.

Blocker filtering low-noise amplifier for SAW-less Bluetooth receiver system

2009 ◽  
Vol 1 (5) ◽  
pp. 447-452 ◽  
Author(s):  
Heesong Seo ◽  
Hyejeong Song ◽  
Changjoon Park ◽  
Jehyung Yoon ◽  
Inyoung Choi ◽  
...  
Keyword(s):  
Noise Figure ◽  
Narrow Band ◽  
Notch Filter ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Receiver System ◽  
The Common ◽  
Noise Amplifier ◽  
A Current

A 2.4 GHz CMOS blocker filtering low-noise amplifier (BF-LNA) suitable for Bluetooth™ application is presented. The circuit employs a differential amplifier topology with a current mirror active load and a notch filter. Each path amplifies differentially with the common mode input signal, but there is a notch filter rejecting only the wanted signal at one path. By subtracting the two signals from each path, the large interferers are rejected and only the wanted signal is amplified. Therefore, it becomes a narrow-band amplifier with blocker filtering capability, realizing a receiver system without need of the off-chip SAW filter. The BF-LNA is designed using a 0.13-μm CMOS process. The measured performances are a gain of 11.4 dB, and a noise figure of 1.85 dB. Attenuation levels at 400 MHz apart from the target frequency are −13 and −29 dBc at each sideband. The P1dB,in and IIP3 are −8.2 and 1.46 dBm, respectively. The proposed BF-LNA can reject large interferers at the front-end of the receiver system with a good noise figure.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

A Highly-Integrated, Switchless and Baluns-Embedded Transceiver with a Differential Structure for C-Band Radar Application

2019 ◽  
Vol 29 (10) ◽  
pp. 2050160
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Zhennan Li ◽  
Zengqi Wang ◽  
Meng Zhang
Keyword(s):  
Output Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Image Rejection ◽  
Rf Switch ◽  
Differential Structure ◽  
Noise Amplifier ◽  
Image Rejection Ratio ◽  
Better Than

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6[Formula: see text]GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-[Formula: see text]m CMOS process. The receiver achieves 6.9-dB NF, [Formula: see text]7.5-dBm IIP3 and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41[Formula: see text]dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106[Formula: see text]mA in the Rx mode and 141[Formula: see text]mA in the Tx mode from the 3.3-V power supply.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

A Fully Integrated 5.2-GHz CMOS Variable Gain LNA for 802.11a WLAN

2012 ◽  
Vol 433-440 ◽  
pp. 5579-5583
Author(s):  
Ji Hai Duan ◽  
Chun Lei Kang
Keyword(s):  
Power Supply ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Small Signal ◽  
Fully Integrated ◽  
Variable Gain ◽  
Noise Amplifier

A fully integrated 5.2GHz variable gain low noise amplifier (VGLNA) in a 0.18μm CMOS process is proposed in this paper. The VGLAN can achieve a maximum small signal gain of 17.85 dB within the noise figure (NF) of 2.04 dB and a minimum gain of 2.04 dB with good input return loss. The LNA’s P1dB in the high gain mode is -17.5 dBm. The LAN consumes only 14.58 mW from a 1.8V power supply.

STUDY OF PARASITIC CAPACITANCE EFFECT ON NOISE FIGURE OF IDCLNA IN DEEP SUBMICRON CMOS TECHNOLOGIES

2014 ◽  
Vol 23 (05) ◽  
pp. 1450058
Author(s):  
S. MANJULA ◽  
D. SELVATHI
Keyword(s):  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Current Gain ◽  
Cmos Process ◽  
Short Channel ◽  
Trade Offs ◽  
Noise Amplifier ◽  
The Impact

Low noise amplifier (LNA) is an important component in RF receiver front end. An inductively degenerated cascode low noise amplifier (IDCLNA) is mostly preferred for producing good trade-offs such as high gain, low noise figure (NF), high reverse isolation and low power consumption for narrowband applications. This IDCLNA structure is also used to reduce the gate induced noise on the noise performance by inserting the capacitance in parallel with the gate-to-source capacitance of main transistor. Usually, the parasitic overlap capacitances can impose serious constraints on achievable performance and is taken into account in IDCLNA. In this paper, IDCLNA is designed at a frequency of 2.4 GHz with analyzing the impact of parasitic overlap capacitances on IDCLNA in terms of unity current gain frequency (f T ) which will affect the NF of IDCLNA and simulated using 130 nm, 90 nm and 65 nm CMOS technologies. The NF of IDCLNA with and without parasitic overlap capacitances are analyzed and compared for different short channel CMOS processes. Simulation results show that the parasitic overlap capacitances have advantageous to reduce the gate induced noise in IDCLNA for 130-nm CMOS process for 2.4 GHz applications.

A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

2013 ◽  
Vol 22 (02) ◽  
pp. 1250088 ◽  
Author(s):  
MERIAM BEN AMOR ◽  
MOURAD LOULOU ◽  
SEBASTIEN QUINTANEL ◽  
DANIEL PASQUET
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Range ◽  
Fully Integrated ◽  
Input Matching ◽  
Noise Amplifier ◽  
Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

A CMOS LNA Partially Degenerated Topology Proposal Using Active Inductors

2017 ◽  
Vol 26 (05) ◽  
pp. 1750078
Author(s):  
E. V. V. Cambero ◽  
C. E. Capovilla ◽  
I. R. S. Casella ◽  
R. R. Munoz ◽  
H. X. Araujo
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Active Area ◽  
Technical Feasibility ◽  
Active Inductors ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Compact Design

This paper presents the design of a CMOS low-noise amplifier (LNA) with partial inductive degeneration using active inductors in [Formula: see text]m technology. Both, the inductor of the partial degeneration and the load inductor, are actives. The inductors configurations are cascode with feedback resistance and Wu folded compact. The LNA has a gain of 13.2[Formula: see text]dB and a noise figure of 4.7[Formula: see text]dB at 1.8[Formula: see text]GHz. The layout has an active area of [Formula: see text]. The results are satisfactory, validating the compact design and demonstrating the technical feasibility of this proposed topology.

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