scholarly journals The Application of Simple and Easy to Implement Decoupling Pulse Scheme Combinations to Effect Decoupling of Large J Values with Reduced Artifacts

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Karel D. Klika
Keyword(s):  
Low Power ◽  
Pulse Width ◽  
Continuous Wave ◽  
Coupling Constant ◽  
Nmr Spectrum ◽  
Composite Pulse ◽  
Adiabatic Pulse ◽  
Large Bandwidth ◽  
Standard Pulse

Of the various problems in decoupling one nucleus type from another using standard decoupling pulse schemes for broadband decoupling, a particular challenge is to effect full, artifact-free decoupling when the size of the coupling constant is very large. Herein it is demonstrated that 1H decoupling of the 31P NMR spectrum of diethyl phosphonate {HP(=O)(OCH2CH3)2} can be accomplished with reduced artifacts despite the large JH,P1 value of 693 Hz by using a combination of decoupling pulse schemes involving continuous-wave (CW) irradiation and either adiabatic-pulse decoupling (APD), MPF decoupling, or traditional composite-pulse decoupling (CPD) schemes such as WALTZ or GARP. The considered strategy is simple, efficient, and easy to implement on most instruments. The best result was attained for a combination of CW and CPD using GARP with a standard pulse width of 60 μs. Altogether, the advantages of the methodology include low power requirements, complete decoupling, tolerance of a range of large J values, large bandwidth for normal-sized J values, and the suppression of sidebands.

scholarly journals Compact CH4 sensor system based on a continuous-wave, low power consumption, room temperature interband cascade laser

2016 ◽  
Vol 108 (1) ◽  
pp. 011106 ◽  
Author(s):  
Lei Dong ◽  
Chunguang Li ◽  
Nancy P. Sanchez ◽  
Aleksander K. Gluszek ◽  
Robert J. Griffin ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Room Temperature ◽  
Continuous Wave ◽  
Sensor System ◽  
Low Power Consumption ◽  
Interband Cascade Laser

Stable continuous-wave mode-locked laser from a 1645 nm Er:YAG ceramic oscillator

2022 ◽  
Author(s):  
Yangyu Liu ◽  
Xue Cao ◽  
AnHua Xian ◽  
Guangmiao Liu ◽  
Wei zhou ◽  
...  
Keyword(s):  
Solid State ◽  
Pulse Width ◽  
Peak Power ◽  
Continuous Wave ◽  
Modulation Depth ◽  
Average Power ◽  
Mode Locking ◽  
Wave Mode ◽  
Semiconductor Saturable Absorber ◽  
Continuous Wave Mode

Abstract We demonstrate stable continuous-wave mode-locking (CWML) pulses around 1645nm by employing the home-made Er:YAG ceramic. By using a fiber laser and semiconductor saturable absorber mirror (SESAM) with modulation depth of 1.2%, we get ML pulses with the output average power up to 815 mW, the pulse width shortened as ~4 ps, and the peak power of 1.8 kW. With the SESAM of modulation depth of 2.4%, the second-order harmonic ML pulses were also obtained. As far as we know, this is the first report of CWML from Er3+-doped ceramics and also the shortest pulse duration in Er3+-doped solid-state oscillators.

Thrust Generation with Low-Power Continuous-Wave Laser and Aluminum Foil Interaction

2010 ◽  
Author(s):  
Hideyuki Horisawa ◽  
Sota Sumida ◽  
Ikkoh Funaki ◽  
Claude Phipps ◽  
Kimiya Komurasaki ◽  
...  
Keyword(s):  
Low Power ◽  
Continuous Wave ◽  
Aluminum Foil ◽  
Continuous Wave Laser ◽  
Thrust Generation ◽  
Wave Laser

A LOW-POWER PULSE WIDTH CODING SCHEME FOR COMMUNICATION RECEIVER SYSTEMS

2012 ◽  
Vol 1 (1) ◽  
Author(s):  
Vyasa Sai ◽  
Ajay Ogirala ◽  
Marlin H. Mickle
Keyword(s):  
Low Power ◽  
Pulse Width ◽  
Power Pulse ◽  
Coding Scheme

3D Integration of Wide IO Memory Cube Stacking to 28 nm Logic Chip with High Density TSV through a Fabless Supplier Chain

2012 ◽  
Vol 2012 (1) ◽  
pp. 000018-000022
Author(s):  
S.Q. Gu ◽  
D.W. King ◽  
V. Ramachandran ◽  
B. Henderson ◽  
U. Ray ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Density ◽  
Temperature Cycle ◽  
Large Bandwidth ◽  
Supplier Chain ◽  
Chip Fabrication ◽  
Logic Process ◽  
Detrimental Impact ◽  
28 Nm

Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices. In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.

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