scholarly journals Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material

2020 ◽  
Vol 18 (2) ◽  
pp. 724
Author(s):  
Ameer F. Roslan ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
K. E. Kaharudin ◽  
I. Ahmad
Keyword(s):  
Performance Improvement ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Metal Gate ◽  
High Permittivity ◽  
Minimum Requirement ◽  
Technology Roadmap ◽  
High K ◽  
Low Performance ◽  
High K Dielectric

<p><span>In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance <br /> (LP) technology. </span></p>

scholarly journals High-K dielectric sulfur-selenium alloys

2019 ◽  
Vol 5 (5) ◽  
pp. eaau9785 ◽  
Author(s):  
Sandhya Susarla ◽  
Thierry Tsafack ◽  
Peter Samora Owuor ◽  
Anand B. Puthirath ◽  
Jordan A. Hachtel ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Metal Oxides ◽  
High Dielectric Constant ◽  
Dielectric Material ◽  
Dielectric Strength ◽  
Dielectric Materials ◽  
High K ◽  
Device Applications ◽  
High K Dielectric ◽  
High Dielectric

Upcoming advancements in flexible technology require mechanically compliant dielectric materials. Current dielectrics have either high dielectric constant, K (e.g., metal oxides) or good flexibility (e.g., polymers). Here, we achieve a golden mean of these properties and obtain a lightweight, viscoelastic, high-K dielectric material by combining two nonpolar, brittle constituents, namely, sulfur (S) and selenium (Se). This S-Se alloy retains polymer-like mechanical flexibility along with a dielectric strength (40 kV/mm) and a high dielectric constant (K = 74 at 1 MHz) similar to those of established metal oxides. Our theoretical model suggests that the principal reason is the strong dipole moment generated due to the unique structural orientation between S and Se atoms. The S-Se alloys can bridge the chasm between mechanically soft and high-K dielectric materials toward several flexible device applications.

Performance Improvement of Pi-gate SOI MOSFET Transistor using High-k Dielectric with Metal Gate

2015 ◽  
Vol 62 (3) ◽  
pp. 331-338 ◽  
Author(s):  
Fatima Zohra Rahou ◽  
A. Guen Bouazza ◽  
B. Bouazza
Keyword(s):  
Performance Improvement ◽  
Metal Gate ◽  
Soi Mosfet ◽  
High K ◽  
High K Dielectric

scholarly journals Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

2021 ◽  
Vol 11 (5) ◽  
pp. 3882
Author(s):  
Hakkee Jung ◽  
Byungon Kim
Keyword(s):  
Dielectric Material ◽  
Dielectric Materials ◽  
Double Gate ◽  
Short Channel ◽  
Current Ratio ◽  
Arithmetic Average ◽  
High K ◽  
Double Gate Mosfet ◽  
High K Dielectric ◽  
High Dielectric

<span>The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO<sub>2</sub>/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. </span><span>The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 10<sup>4</sup> or less is shown for SiO<sub>2</sub>, but the on-off current ratio for TiO<sub>2</sub> (<em>k</em>=80) increases to 10<sup>7</sup> or more.</span>

scholarly journals 3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect

2018 ◽  
Vol 12 (3) ◽  
pp. 1358
Author(s):  
Ameer F. Roslan ◽  
F. Salehuddin ◽  
A.S. M.Zain ◽  
K.E. Kaharudin ◽  
H. Hazura ◽  
...  
Keyword(s):  
Leakage Current ◽  
Electrical Characterization ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
3D Design ◽  
Drive Current ◽  
Minimum Requirement ◽  
Technology Roadmap ◽  
Low Performance

<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>

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