Design of AES Algorithm for 128/192/256 Key Length in FPGA

2014 ◽  
Vol 3 (2) ◽  
pp. 49
Author(s):  
Pravin V. Kinge ◽  
S.J. Honale ◽  
C.M. Bobade
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Image Data ◽  
Data Encryption ◽  
Encrypted Image ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Hardware Description ◽  
Key Length

<p class="p0">The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for  data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 &amp; 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL).</p>

Design of AES Pipelined Architecture for Image Encryption/Decryption Module

2014 ◽  
Vol 3 (3) ◽  
pp. 114
Author(s):  
Pravin V. Kinge ◽  
S.J. Honale ◽  
C.M. Bobade
Keyword(s):  
Image Encryption ◽  
Integrated Circuit ◽  
High Speed ◽  
Transmission Rate ◽  
Image Data ◽  
Limited Bandwidth ◽  
Encrypted Image ◽  
Aes Algorithm ◽  
Pipelined Architecture ◽  
Encryption And Decryption

The relentless growth of Internet and communication technologies has made the extensive use of images unavoidable. The specific characteristics of image like high transmission rate with limited bandwidth, redundancy, bulk capacity and correlation among pixels makes standard algorithms not suitable for image encryption. In order to overcome these limitations for real time applications, design of new algorithms that require less computational power while preserving a sufficient level of security has always been a subject of interest. Here Advanced Encryption Standard (AES),as the most widely used encryption algorithm in many security applications. AES standard has different key size variants, where longer bit keys provide more secure ciphered text output. The available AES algorithm is used for  data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to Pipelined AES algorithm through Textio, to obtain the encrypted image. and the encrypted image is the input to Pipelined AES Decryption to get the original image. This project proposed to implement the 128,192 &amp; 256 bit Pipelined AES algorithm for image encryption and decryption, also to compare the latency , efficiency, security, frequency &amp; throughput . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language.

scholarly journals Advanced Encryption Standard for Data Encryption using EDK Environment in FPGA

2019 ◽  
Vol 8 (4) ◽  
pp. 11969-11972
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Efficient Processing

now a day’s VLSI is developing technology as predicted by Moors law which is drastically increasing as per demand one of that is data security for efficient processing so, data encryption and decryption are major play in security for this an advanced encryption standard is there which uses reconfigurable hardware process in this paper field programmable gate arrays (FPGAs) kit of Xilinx based platform in which spartan3E EDK kit is used. Here we analyze the speed of AES algorithm by using this EDK environment where obvious high speed is considerable and with power consumption and throughput exemptions. With micro blaze soft core processer we implement our algorithm of AES by using c coding we configure the hardware structure. EDK tool with one round operation is done and both area utilization and throughput are observed as we are familiar that when area reduces power consumption also reduces.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

Power and Vibration of Electrostatic Precipitator Control Based on FPGA

2014 ◽  
Vol 1037 ◽  
pp. 244-247
Author(s):  
Zi Sheng Zhang ◽  
Chun Sheng Wang ◽  
Yi Wang ◽  
Zhan You Wang ◽  
Deng Yuan Song
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Electrostatic Precipitator ◽  
Description Language ◽  
Simulation Test ◽  
High Voltage Power Supply ◽  
Optimization Control ◽  
Field Programmable ◽  
Hardware Description ◽  
Fpga Chip

In order to improve the automation level of the electrostatic precipitator, we used Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) language to compile, emulate and optimize the control system of power source and vibration. In the design of Quartus platform, we used EP1C3T144C8 Field Programmable Gate Array (FPGA) chip to realize high voltage power supply, alarm and protection system. We also realized the compilation and simulation test of each part’s function of 20 s rapping and 40 min rapping cycle. At the same time, we recorded the waveform of simulation. It demonstrated that the validity of the relevant VHDL compilation. We used this method to achieve the optimization control of the electrostatic precipitator operating parameters. It has a strong practicability.

scholarly journals Support Vector Machine working on FPGA and the segmentation method of brain MR screening

2017 ◽  
Vol 4 (3) ◽  
pp. 120 ◽  
Author(s):  
Fatih Şişik ◽  
Eser Sert
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Support Vector ◽  
Segmentation Method ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Very High

Alan Programlanabilir Kapı Dizileri (Field Programmable Gate Array-FPGA) programlanabilir sayısal bloklar ve bağlantılarını içeren cihazlar olup çok esnek ve hızlı çalışabilme özelliklerine sahiptir. Programlanabilen bu sayısal kapılar sayesinde karmaşık tasarımlar kolay bir şekilde geliştirilebilmektedir. FPGA’lar küçük boyutlarda olup bilgisayardan bağımsız mobil olarak ve bilgisayarlardan daha yüksek hızlarda çalışabilmektedirler. Veri madenciliğinin görevlerinden biri olan sınıflandırma probleminin çözümü için geliştirilmiş önemli makine öğrenimi algoritmalarından biri Destek Vektör Makineleri’ dir. Literatürde Destek Vektör Makineleri’ nin diğer birçok tekniğe göre daha başarılı sonuçlar verdiği kanıtlanmıştır. Tümör analizi, yüz tanıma, robotik göz oluşturma gibi konular, araştırmacıların görüntü işleme alanında yoğun olarak üzerinde çalıştıkları güncel, önemli ve zor problemlerden bazılarıdır. Bilgisayarda yapılan tümör analizinde, grafik ve resimlerin işlenmesinde yavaş işlem yapma ve aynı zamanda mobil olmama sorunlarından, FPGA donanımı ile görüntü işlemede bu sorunların üstesinden gelinmektedir. Bu çalışmada FPGA donanımında çalışan destek vektör makinası kullanılarak daha gerçekçi tümör analizi yapılarak tümörlü bölgelerin bulunması ve gerekli analiz sonuçlarının gösterilmesi amaçlanmaktadır. Böylece sağlık alanında da kullanılabilecek yararlı bir donanımın tasarımı gerçekleştirilecektir. Dolayısıyla gömülü sistemlerle anlatılan bu işlem süreçlerini gerçekleştiren çalışma sayısı çok az olduğundan çalışma özgün değer taşımaktadır. Buna ek olarak, FPGA’ ya özgü donanım tanımlama dillerinden biri olan Çok Yüksek Hızlı Tümleşik Devre Tanımlama Dili (Very High Speed Integrated Circuit  Hardware Description Language- VHDL) kullanılacaktır. Bölütleme sonucunun değerlendirilmesi için Uniformity Measure (UM) kullanılmıştır. UM değerlendirme sonucunun başarılı olduğu görülmüştür. Anahtar Kelimeler: Alan Programlanabilir Kapı Dizileri, FPGA, çok yüksek hızlı tümleşik devre tanımlama dili, vhdl, segmentasyon, destek vektör makinesi

Design and Implementation of Adaptive FIR filter using Systolic Architecture

2014 ◽  
Vol 3 (2) ◽  
pp. 54
Author(s):  
Ravi H Bailmare ◽  
S.J. Honale ◽  
Pravin V Kinge
Keyword(s):  
Mean Square Error ◽  
Integrated Circuit ◽  
High Speed ◽  
Minimum Mean Square Error ◽  
Weight Vector ◽  
Internet Technology ◽  
Mean Square ◽  
Systolic Architecture ◽  
Field Programmable ◽  
Hardware Description

<p>The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used. Systolic architecture is an arrangement of processor where data flows synchronously across array element. This project demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of pipelining and parallel processing in to the systolic architecture the computing speed increases.</p>

scholarly journals Performance analysis of number theoretic transform-based convolution using field programmable gate array

2018 ◽  
Vol 7 (2.8) ◽  
pp. 204
Author(s):  
G A.E Satish Kumar
Keyword(s):  
Performance Analysis ◽  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Convolution Operation ◽  
The Matrix ◽  
Field Programmable ◽  
High Power Consumption ◽  
Hardware Description ◽  
Very High

This paper presents the convolution operation based on the Number Theoretic Transfom for two n=8 input sequences. The convolution of two n-point sequences using Fast Fourier Transform exhibits design complexity leading to high power consumption. The Number Theoretic Transform utilizes the matrix of modulus values to evaluate the convolution. The Number Theoretic Transform is as an integer transform which makes the design comparatively simple. The convolution based Number Theoretic Transform is developed using the Very High Speed Integrated Circuit Hardware Description language.Also the real time implementation of the proposed method is validated by the Xilinx Spartan FPGA family devices. The performance analysis of power, speed and area are evaluated and compared with 3A DSP FPGA and Virtex 6 FPGA devices.

From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging

2012 ◽  
Vol 588-589 ◽  
pp. 777-780
Author(s):  
Cheng Shion Shieh
Keyword(s):  
Wind Power ◽  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Flow Chart ◽  
Charging Control ◽  
Field Programmable ◽  
Hardware Description ◽  
Fpga Chip ◽  
Gate Array

While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presented to illustrate the effectiveness of the proposed charging flow chart.

scholarly journals Enhanced RSA Cryptosystem based on Multiplicity of Public and Private Keys

2018 ◽  
Vol 8 (5) ◽  
pp. 3949
Author(s):  
Ahmed Eskander Mezher
Keyword(s):  
High Speed ◽  
Data Encryption ◽  
Advanced Technology ◽  
Security And Privacy ◽  
Public And Private ◽  
Rsa Algorithm ◽  
Cryptographic Algorithm ◽  
Important Concern ◽  
Encryption And Decryption ◽  
Key Length

Security is one of the most important concern to the information and data sharing for companies, banks, organizations and government facilities. RSA is a public cryptographic algorithm that is designed specifically for authentication and data encryption. One of the most powerful reasons makes RSA more secure is that the avoidance of key exchange in the encryption and decryption processes. Standard RSA algorithm depends on the key length only to protect systems. However, RSA key is broken from time to another due to the development of computers hardware such as high speed processors and advanced technology. RSA developers have increased a key length or size of a key periodically to maintain a high security and privacy to systems that are protected by the RSA. In this paper, a method has been designed and implemented to strengthen the RSA algorithm by using multiple public and private keys. Therefore, in this method the security of RSA not only depends on the key size, but also relies on the multiplicity of public and private keys.

Step Motor Control Based on FPGA

2013 ◽  
Vol 397-400 ◽  
pp. 1226-1229
Author(s):  
Juan Zhu ◽  
Yue Chen
Keyword(s):  
Motor Control ◽  
Control System ◽  
Integrated Circuit ◽  
High Speed ◽  
Step Motor ◽  
Single Chip ◽  
Field Programmable ◽  
Hardware Description ◽  
Motor Control System ◽  
Hardware Circuit

Design a step motor control system based on Field Programmable Gate Array (FPGA). Give the hardware circuit of this system and the program based on very high speed integrated circuit hardware description language (VHDL). Compared to step motor control system based on single chip microcomputer, the processing speed of this system is faster.

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