scholarly journals NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm

2018 ◽  
Vol 6 (2) ◽  
pp. 105
Author(s):  
A. Kalimuthu ◽  
M. Karthikeyan
Keyword(s):  
Resource Sharing ◽  
Clustering Algorithms ◽  
Font Size ◽  
Core System ◽  
Mesh Structure ◽  
Low Area ◽  
Area Overhead ◽  
Overall Performance ◽  
On Chip ◽  
Many Core

<span style="font-size: 9pt; font-family: 'Times New Roman', serif;">A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique</span>

scholarly journals Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
Alireza Monemi ◽  
Chia Yee Ooi ◽  
Muhammad Nadzir Marsono
Keyword(s):  
High Performance ◽  
Clock Cycle ◽  
Network On Chip ◽  
Operating Frequency ◽  
Low Latency ◽  
Core System ◽  
Low Area ◽  
Area Overhead ◽  
Logic Cells ◽  
On Chip

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

A Fault-Tolerant Deflection Routing for Network-on-Chip

2016 ◽  
Vol 26 (03) ◽  
pp. 1750037 ◽  
Author(s):  
Xiaofeng Zhou ◽  
Lu Liu ◽  
Zhangming Zhu
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Deflection Routing ◽  
Core System ◽  
Routing Schemes ◽  
Routing Performance ◽  
Layout Area ◽  
On Chip ◽  
Many Core ◽  
Redundant Fault

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.

Thermal Investigation Into Power Multiplexing for Homogeneous Many-Core Processors

2012 ◽  
Vol 134 (6) ◽  
Author(s):  
Man Prakash Gupta ◽  
Minki Cho ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Thermal Management ◽  
Power Distribution ◽  
Peak Temperature ◽  
Management Technique ◽  
Time Intervals ◽  
Regular Time ◽  
Overall Performance ◽  
On Chip ◽  
Many Core ◽  
Power Configuration

In this paper, a proactive thermal management technique called “power multiplexing” is explored for many-core processors. Power multiplexing involves redistribution of the locations of active cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic, and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Power configuration on the chip is characterized by a parameter called “proximity index” which emerges as an important parameter to represent the spatial power distribution on a chip. We also notice that the overall performance of the chip could be improved by 10% using global multiplexing.

A Long-wire-connected and Multi-channel 3D Network-on-chip Design for Many-core System

2013 ◽  
Vol 11 (12) ◽  
Author(s):  
Tan Hai ◽  
Shahnawaz Talpur ◽  
Amir Mahmood Soomro ◽  
Chen Hong Mao
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Core System ◽  
3D Network ◽  
On Chip ◽  
Many Core

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

2017 ◽  
Vol 54 ◽  
pp. 60-74 ◽  
Author(s):  
Alireza Monemi ◽  
Jia Wei Tang ◽  
Maurizio Palesi ◽  
Muhammad N. Marsono
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Core System ◽  
On Chip ◽  
Many Core

Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs

2016 ◽  
Author(s):  
Zheng Wang ◽  
Alessandro Littarru ◽  
Emmanuel Ikechukwu Ugwu ◽  
Shazia Kanwal ◽  
Anupam Chattopadhyay
Keyword(s):  
Fault Tolerant ◽  
System On Chip ◽  
Chip Design ◽  
Core System ◽  
On Chip ◽  
Many Core

scholarly journals Efficient Communication Protection of Many-Core Systems against Active Attackers

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 238
Author(s):  
Sadia Moriam ◽  
Elke Franz ◽  
Paul Walther ◽  
Akash Kumar ◽  
Thorsten Strufe ◽  
...  
Keyword(s):  
Network Coding ◽  
Analytical Approach ◽  
Estimation Error ◽  
Third Party ◽  
Authentication Codes ◽  
Core System ◽  
Area Overhead ◽  
Active Attacks ◽  
Many Core ◽  
The Impact

Many-core system-on-chips, together with their established communication infrastructures, Networks-on-Chip (NoC), are growing in complexity, which encourages the integration of third-party components to simplify and accelerate production processes. However, this also adversely exposes the surface for attacks through the injection of hardware Trojans. This work addresses active attacks on NoCs and focuses on the integrity and availability of transmitted data. In particular, we consider the modification and/or dropping of data during transmission as active attacks that might be performed by malicious routers. To mitigate the impact of such active attacks, we propose two lightweight solutions that respect the performance constraints of NoCs. Assuming the presence of symmetric keys, these approaches combine lightweight authentication codes for integrity protection with network coding for increased efficiency and robustness. The proposed solutions prevent undetected modifications and significantly increase availability through a reliable detection of attacks. The efficiency of these solutions is investigated in different scenarios using cycle-accurate simulations and the area overhead is analyzed relative to state-of-the-art many-core system. The results demonstrate that one authentication scheme with network coding protects the integrity of data to a low residual error of 1.36% at 0.2 attack probability with an area overhead of 2.68%. For faster and more flexible evaluation, an analytical approach is developed which is validated against the cycle-accurate simulations. The analytical approach is more than 1000× faster while having a maximum estimation error of 5%. Moreover, the analytical model provides a deeper insight into the system’s behavior. For example, it reveals which factors influence the performance parameters.

scholarly journals Networks on Chips: Structure and Design Methodologies

2012 ◽  
Vol 2012 ◽  
pp. 1-15 ◽  
Author(s):  
Wen-Chung Tsai ◽  
Ying-Cherng Lan ◽  
Yu-Hen Hu ◽  
Sao-Jie Chen
Keyword(s):  
High Performance ◽  
Chip Multiprocessors ◽  
Multiprocessor System ◽  
Communication Performance ◽  
Core System ◽  
Traditional System ◽  
On Chip ◽  
Many Core ◽  
Bus Architecture

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

Many-core System-on-Chip: architectures and applications

2016 ◽  
Vol 43 ◽  
pp. 1-3 ◽  
Author(s):  
Mohamed Bakhouya ◽  
Masoud Daneshtalab ◽  
Maurizio Palesi ◽  
Hassan Ghasemzadeh
Keyword(s):  
System On Chip ◽  
Core System ◽  
On Chip ◽  
Many Core

scholarly journals Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 811
Author(s):  
Suleman Alnatheer ◽  
Mohammed Altaf Ahmed
Keyword(s):  
Current System ◽  
Repair Rate ◽  
Optimal Method ◽  
Low Area ◽  
Area Overhead ◽  
Memory Faults ◽  
On Chip ◽  
Almost All ◽  
Embedded Memories ◽  
To Receive

The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

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