Improved Mobility and Bias Stability of Thin Film Transistors Using the Double-Layer a-InGaZnO/a-InGaZnO:N Channel

2016 ◽  
Vol 16 (4) ◽  
pp. 3659-3663
Author(s):  
H Yu ◽  
L Zhang ◽  
X. H Li ◽  
H. Y Xu ◽  
Y. C Liu
Keyword(s):  
Thin Film ◽  
Double Layer ◽  
Thin Film Transistors ◽  
Carrier Transport ◽  
Single Layer ◽  
Channel Structure ◽  
Gate Insulator ◽  
Large Area ◽  
Threshold Voltage Shift ◽  
High Carrier

The amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) were demonstrated based on a double-layer channel structure, where the channel is composed of an ultrathin nitrogenated a-IGZO (a-IGZO:N) layer and an undoped a-IGZO layer. The double-layer channel device showed higher saturation mobility and lower threshold-voltage shift (5.74 cm2/Vs, 2.6 V) compared to its single-layer counterpart (0.17 cm2/Vs, 7.23 V). The improvement can be attributed to three aspects: (1) improved carrier transport properties of the channel by the a-IGZO:N layer with high carrier mobility and the a-IGZO layer with high carrier concentration, (2) reduced interfacial trap density between the active channel and the gate insulator, and (3) higher surface flatness of the double-layer channel. Our study reveals key insights into double-layer channel, involving selecting more suitable electrical property for back-channel layer and more suitable interface modification for active layer. Meanwhile, room temperature fabrication amorphous TFTs offer certain advantages on better flexibility and higher uniformity over a large area.

Investigation on the Electrical Stability of 5,11-Bis(triethylsilylethynyl)anthradithiophene Thin-Film Transistors

2021 ◽  
Vol 21 (3) ◽  
pp. 1754-1760
Author(s):  
Joel Ndikumana ◽  
Jyothi Chintalapalli ◽  
Jin-Hyuk Kwon ◽  
Jin-Hyuk Bae ◽  
Jaehoon Park
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Ambient Air ◽  
Gate Insulator ◽  
Hydroxyl Groups ◽  
Electrical Stability ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Domain Boundaries

We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.

Fabrication of Stretchable Organic–Inorganic Hybrid Thin-Film Transistors on Polyimide Stiff-Island Structures

2015 ◽  
Vol 15 (10) ◽  
pp. 7526-7530 ◽  
Author(s):  
Soon-Won Jung ◽  
Jae Bon Koo ◽  
Chan Woo Park ◽  
Bock Soon Na ◽  
Ji-Young Oh ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Vinylidene Fluoride ◽  
Channel Structure ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
Hybrid Thin Film ◽  
Inorganic Hybrid ◽  
Poly Vinylidene Fluoride

In this study, stretchable organic–inorganic hybrid thin-film transistors (TFTs) are fabricated on a polyimide (PI) stiff-island/elastomer substrate using blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) and oxide semiconductor In-Ga-Zn-O as the gate dielectric and semiconducting layer, respectively. Carrier mobility, Ion/Ioff ratio, and subthreshold swing (SS) values of 6.1 cm2 V−1 s−1, 107, and 0.2 V/decade, respectively, were achieved. For the hybrid TFTs, the endurable maximum strain without degradation of electrical properties was approximately 49%. These results correspond to those obtained in the first study on fabrication of stretchable hybrid-type TFTs on elastomer substrate using an organic gate insulator and oxide semiconducting active channel structure, thus indicating the feasibility of a promising device for stretchable electronic systems.

100-nm Channel Length a-Si:H Vertical Thin Film Transistors

2004 ◽  
Vol 814 ◽  
Author(s):  
Isaac Chan ◽  
Arokia Nathan
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Vertical Channel ◽  
Channel Length ◽  
Channel Structure ◽  
Large Area ◽  
Short Channel ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Channel Effects

AbstractThis paper reports on hydrogenated amorphous silicon (a-Si:H) vertical thin film transistors (VTFTs) with channel length of 100 nm, using conventional planar TFT processing technology. The device has a fully self-aligned vertical channel structure, which is highly insensitive to the non-uniformity of reactive ion etching (RIE). Therefore, the VTFT process is very suitable for large-area electronics. Presently, we can demonstrate VTFTs with remarkable ON/OFF current ratio of more than 108, low leakage current down to 1 fA, and good subthreshold slope of 0.8 V/dec at Vd = 1.5 V. The impacts of contemporary device issues, such as short-channel effects and contact resistance, on the performance of short-channel VTFTs and suggested avenues for improvement are discussed.

scholarly journals Quantum Confinement Effect in Amorphous In–Ga–Zn–O Heterojunction Channels for Thin-Film Transistors

Materials ◽  
2020 ◽  
Vol 13 (8) ◽  
pp. 1935 ◽  
Author(s):  
Daichi Koretomo ◽  
Shuhei Hamada ◽  
Yusaku Magari ◽  
Mamoru Furuta
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Quantum Confinement ◽  
Carrier Transport ◽  
Simulation Analysis ◽  
Quantum Confinement Effect ◽  
Energy Band Diagram ◽  
Confinement Effect ◽  
Gate Insulator ◽  
Conduction Band Offset

Electrical and carrier transport properties in In–Ga–Zn–O thin-film transistors (IGZO TFTs) with a heterojunction channel were investigated. For the heterojunction IGZO channel, a high-In composition IGZO layer (IGZO-high-In) was deposited on a typical compositions IGZO layer (IGZO-111). From the optical properties and photoelectron yield spectroscopy measurements, the heterojunction channel was expected to have the type–II energy band diagram which possesses a conduction band offset (ΔEc) of ~0.4 eV. A depth profile of background charge density indicated that a steep ΔEc is formed even in the amorphous IGZO heterojunction interface deposited by sputtering. A field effect mobility (μFE) of bottom gate structured IGZO TFTs with the heterojunction channel (hetero-IGZO TFTs) improved to ~20 cm2 V−1 s−1, although a channel/gate insulator interface was formed by an IGZO−111 (μFE = ~12 cm2 V−1 s−1). Device simulation analysis revealed that the improvement of μFE in the hetero-IGZO TFTs was originated by a quantum confinement effect for electrons at the heterojunction interface owing to a formation of steep ΔEc. Thus, we believe that heterojunction IGZO channel is an effective method to improve electrical properties of the TFTs.

NANOCRYSTALLINE SILICON THIN FILM TRANSISTORS FOR HIGH PERFORMANCE LARGE AREA ELECTRONICS

2008 ◽  
Vol 18 (04) ◽  
pp. 1055-1068
Author(s):  
MOHAMMAD R. ESMAEILI-RAD ◽  
HYUN JUNG LEE ◽  
ANDREI SAZONOV ◽  
AROKIA NATHAN
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
High Performance ◽  
Nanocrystalline Silicon ◽  
Large Area ◽  
Silicon Thin Film ◽  
Threshold Voltage Shift ◽  
Readout Circuits ◽  
Large Area Electronics

Nanocrystalline silicon ( nc - Si ) thin film transistors (TFTs) have potential for high-performance applications in large area electronics, such as next generation of flat panel displays and medical x-ray imagers, for pixel drivers, readout circuits, as well as complementary channel logic circuits for system-on-panel integration. This potential stems from reduced threshold voltage shift and higher transconductance, compared to amorphous silicon counterpart. In this paper, we discuss various TFT structures, their associated design and performance considerations, including leakage current and threshold voltage stability mechanisms.

CONTROLLING INSTABILITIES OF HYDROGENERATED a-Si:H TFT UNDER BIAS TEMPERATURE STRESSING

2008 ◽  
Vol 22 (04) ◽  
pp. 263-268
Author(s):  
YONG K. LEE
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Amorphous Silicon ◽  
Bias Voltage ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Gate Insulator ◽  
Instability Mechanism ◽  
Device Structure ◽  
Threshold Voltage Shift

The hydrogenerated amorphous silicon a-Si:H thin film transistors TFT with silicon nitride as a gate insulator have been stressed with independently varying gate (Vg), source (Vs), and gate-source (Vgs) bias voltage in order to elucidate the instability mechanism and suggest the new a-Si:H TFT structure. It was found that there was dependency of threshold voltage shift not only on Vgs, but also on Vg and Vs, which had not ever been reported. Its shift amount increased with increasing Vs and/or Vg. In this reports, we suggested the new TFT device structure to eliminate the dependency of Vth shift on Vg and Vs and found that with the new suggested TFT structure, the Vth shift controlling factor can only be Vgs.

Low-Temperature Formation of SiNx Gate Insulator for Thin-Film Transistor Using CAT-CVD Method

1998 ◽  
Vol 508 ◽  
Author(s):  
A. Izumi ◽  
T. Ichise ◽  
H. Matsumura
Keyword(s):  
Thin Film ◽  
Chemical Vapor Deposition ◽  
Silicon Nitride ◽  
Vapor Deposition ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
State Density ◽  
Gate Insulator ◽  
Catalytic Chemical Vapor Deposition ◽  
Silicon Nitride Films

AbstractSilicon nitride films prepared by low temperatures are widely applicable as gate insulator films of thin film transistors of liquid crystal displays. In this work, silicon nitride films are formed around 300 °C by deposition and direct nitridation methods in a catalytic chemical vapor deposition system. The properties of the silicon nitride films are investigated. It is found that, 1) the breakdown electric field is over 9MV/cm, 2) the surface state density is about 1011cm−2eV−1 are observed in the deposition films. These result shows the usefulness of the catalytic chemical vapor deposition silicon nitride films as gate insulator material for thin film transistors.

Wide range modulation of synaptic weight in thin-film transistors with hafnium oxide gate insulator and indium-zinc oxide channel layer for artificial synapse application

Nanoscale ◽  
2021 ◽  
Author(s):  
Keonwon Beom ◽  
Jimin Han ◽  
Hyun-Mi Kim ◽  
Tae-Sik Yoon
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Hafnium Oxide ◽  
Synaptic Weight ◽  
Drain Current ◽  
Gate Insulator ◽  
Channel Layer ◽  
Indium Zinc Oxide ◽  
Wide Range

Wide range synaptic weight modulation with a tunable drain current was demonstrated in thin-film transistors (TFTs) with a hafnium oxide (HfO2−x) gate insulator and an indium-zinc oxide (IZO) channel layer...

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