Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Abstract In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10-16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 1011 has been achieved. The device exhibits a high transconductance of 3.022x10-5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

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Boosting on Current Using Various Source Material for Dual Gate Tunnel Field Effect Transistor

10.46610/jonne.2021.v07i01.001 ◽

2021 ◽

Vol 7 (1) ◽

Author(s):

Priyadarshini N D ◽

Nayana G H ◽

P Vimala

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Field Effect Transistors ◽

Source Material ◽

Oxide Semiconductor ◽

Low Leakage ◽

Low Leakage Current ◽

Dual Gate ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutting-edge low force and super low force semiconductors to substitute the conventional FETs. TFET will be able to provide steep inverse subthreshold swing slope also maintaining a low leakage current, making it an essential structure for limiting the power consumption in Metal Oxide Semiconductor FETs.In this paper, we are simulating different structures of TFET by varying source material to boost the ON current of the device. The different models are designed and simulated using Silvaco TCAD simulator and transfer characteristics are studied.

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Effects of Back-Gate Bias on Subthreshold Swing of Tunnel Field-Effect Transistor

Electronics ◽

10.3390/electronics8121415 ◽

2019 ◽

Vol 8 (12) ◽

pp. 1415 ◽

Cited By ~ 1

Author(s):

Jaehong Lee ◽

Garam Kim ◽

Sangwan Kim

Keyword(s):

Gate Voltage ◽

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistor ◽

Subthreshold Swing ◽

Gate Bias ◽

Back Gate ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Aided Design

In this study, the effects of back-gate bias on the subthreshold swing (S) of a tunnel field-effect transistor (TFET) were discussed. The electrostatic characteristics of the back-gated TFET were obtained using technology computer-aided design (TCAD) simulation and were explained using the concepts of turn-on and inversion voltages. As a result, S decreased, when the back-gate voltage increased; this behavior is attributed to the resultant increase in inversion voltage. In addition, it was found that the on–off current ratio of the TFET increased with a decrease in S due to the back-gate voltage.

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Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor

10.21203/rs.3.rs-359321/v1 ◽

2021 ◽

Author(s):

Dharmender Nishad ◽

Kaushal Nigam ◽

Satyendra Kumar

Keyword(s):

Temperature Sensitivity ◽

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistor ◽

Effect Of Temperature ◽

Double Gate ◽

Extended Source ◽

Temperature Variations ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.

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GeSn/GeSiSn double-heterojunction short channel tunnel field-effect transistor design

Japanese Journal of Applied Physics ◽

10.35848/1347-4065/ab705f ◽

2020 ◽

Vol 59 (3) ◽

pp. 034001

Author(s):

Suyuan Wang ◽

Qiang Wu ◽

Jun Zheng ◽

Bin Zhang ◽

Jianghong Yao ◽

...

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Short Channel ◽

Double Heterojunction ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

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Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽

10.3390/mi10010030 ◽

2019 ◽

Vol 10 (1) ◽

pp. 30 ◽

Cited By ~ 3

Author(s):

Jang Hyun Kim ◽

Hyun Woo Kim ◽

Garam Kim ◽

Sangwan Kim ◽

Byung-Gook Park

Keyword(s):

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistor ◽

Electrical Performance ◽

Control Group ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Tcad Simulation ◽

High Level ◽

Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

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Complementary Trilayer–Bulk Black Phosphorus Heterojunction Tunnel Field-Effect Transistor with Subthermionic Subthreshold Swing

ACS Applied Electronic Materials ◽

10.1021/acsaelm.0c00603 ◽

2020 ◽

Vol 2 (11) ◽

pp. 3491-3496

Author(s):

Seungho Kim ◽

Gyuho Myeong ◽

Jeehoon Park ◽

Taehyuk Jin ◽

Kenji Watanabe ◽

...

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Black Phosphorus ◽

Subthreshold Swing ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

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Gate-controlled MoTe2 homojunction for sub-thermionic subthreshold swing tunnel field-effect transistor

Nano Today ◽

10.1016/j.nantod.2021.101263 ◽

2021 ◽

Vol 40 ◽

pp. 101263

Author(s):

Ngoc Thanh Duong ◽

Chulho Park ◽

Duc Hieu Nguyen ◽

Phuong Huyen Nguyen ◽

Thi Uyen Tran ◽

...

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Subthreshold Swing ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

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Impact of Band-Tails on the Subthreshold Swing of III-V Tunnel Field-Effect Transistor

IEEE Electron Device Letters ◽

10.1109/led.2017.2764873 ◽

2017 ◽

Vol 38 (12) ◽

pp. 1661-1664 ◽

Cited By ~ 13

Author(s):

E. Memisevic ◽

E. Lind ◽

M. Hellenbrand ◽

J. Svensson ◽

L.-E. Wernersson

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Subthreshold Swing ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Band Tails

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Low-leakage current and high-breakdown voltage GaAs-based heterostructure field-effect transistor with In0.5(Al0.66Ga0.34)0.5P Schottky layer

Applied Physics Letters ◽

10.1063/1.125385 ◽

1999 ◽

Vol 75 (22) ◽

pp. 3551-3553 ◽

Cited By ~ 5

Author(s):

Y. S. Lin ◽

W. C. Hsu ◽

C. S. Yang

Keyword(s):

Leakage Current ◽

Breakdown Voltage ◽

Field Effect ◽

Field Effect Transistor ◽

High Breakdown Voltage ◽

Low Leakage ◽

Low Leakage Current ◽

Effect Transistor

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I-Shaped SiGe Fin Tunnel Field-Effect Transistor with High ION/IOFF Ratio

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2020.17794 ◽

2020 ◽

Vol 20 (7) ◽

pp. 4298-4302

Author(s):

Ryoongbin Lee ◽

Junil Lee ◽

Kitae Lee ◽

Soyoun Kim ◽

Sihyun Kim ◽

...

Keyword(s):

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistor ◽

Channel Width ◽

Condensation Process ◽

Performance Improvements ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Aided Design ◽

Effective Channel

In this paper, we propose an I-shaped SiGe fin tunnel field-effect transistor (TFET) and use technology computer aided design (TCAD) simulations to verify the validity. Compared to conventional Fin TFET on the same footprint, a 27% increase in the effective channel width can be obtained with the proposed TFET. The proposed Fin TFET was confirmed to have 300% boosted on-current (I on), 25% reduced subthreshold swing (SS), and 52% lower off-current (I off) than conventional Fin TFET through TCAD simulation results. These performance improvements are attributed to increased effective channel width and enhanced gate controllability of the I-shaped fin structure. Furthermore, the fabrication process of forming an I-shaped SiGe fin is also presented using the SiGe wet etch. By optimizing the Ge condensation process, an I-shaped SiGe fin with a Ge ratio greater than 50% can be obtained.

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