Enhanced Activation of Standard and Cocktail Spike Annealed Junctions with Additional Sub-melt Laser Anneal

AbstractThe advantages of fluorine co-implantation on reducing the deep P junction profile is investigated and commented as a possible valuable solution for further scaling of the NMOS transistors spacer length. On PMOS transistors, Ge+C+B cocktail junctions lead to improved short channel effects control, S/D resistance and performance over the conventional approaches. Additional laser annealing induces a partial dissolution of the doping clusters in the junction and lower the S/D transistors resistance. A performance improvement is demonstrated both for NMOS and PMOS with cocktail junctions activated by spike RTA and additional laser annealing.

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Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors

Advances in Computer and Electrical Engineering - Innovative Applications of Nanowires for Circuit Design ◽

10.4018/978-1-7998-6467-7.ch003 ◽

2021 ◽

pp. 54-70

Author(s):

Raj Kumar ◽

Shashi Bala ◽

Arvind Kumar

Keyword(s):

Performance Analysis ◽

Field Effect ◽

Field Effect Transistors ◽

Ballistic Transport ◽

High Mobility ◽

Short Channel Effects ◽

Short Channel ◽

Comparative Performance ◽

Channel Effects ◽

And Performance

To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.

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A compact quasi 3D threshold voltage modeling and performance analysis of a novel linearly graded binary metal alloy quadruple gate MOSFET for subdued short channel effects

Superlattices and Microstructures ◽

10.1016/j.spmi.2015.01.035 ◽

2015 ◽

Vol 82 ◽

pp. 293-302 ◽

Cited By ~ 16

Author(s):

Saheli Sarkhel ◽

Subir Kumar Sarkar

Keyword(s):

Performance Analysis ◽

Threshold Voltage ◽

Metal Alloy ◽

Short Channel Effects ◽

Short Channel ◽

Binary Metal ◽

Channel Effects ◽

And Performance

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Examining the Short Channel Characteristic and Performance of Triple Material Double Gate Silicon-on-Nothing Metal Oxide Semiconductor Field Effect Transistors with Grading Channel Concentration

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2019.2667 ◽

2019 ◽

Vol 14 (12) ◽

pp. 1672-1679 ◽

Cited By ~ 1

Author(s):

Ningombam Ajit Kumar ◽

Aheibam Dinamani Singh ◽

Nameirakpam Basanta Singh

Keyword(s):

Surface Potential ◽

Field Effect Transistors ◽

Oxide Semiconductor ◽

Double Gate ◽

Short Channel Effects ◽

Parabolic Approximation ◽

Short Channel ◽

Channel Characteristic ◽

Channel Effects ◽

And Performance

A 2D surface potential analytical model of a channel with graded channel triple material double gate (GCTMDG) Silicon-on-Nothing (SON) MOSFET is proposed by intermixing the benefits of triple material in gate engineering and graded doping in the channel. The surface potential distribution function of the GCTMDG SON MOSFET is obtained by solving the Poisson's equation, applying suitable boundary conditions, and using a parabolic approximation method. It is seen in the proposed device that the Short Channel Effects (SCEs) are subdued due to the apprehensible step in the surface potential profile that screen the potential of the drain. The effects of the various device parameters are studied to check the merit of the device. For the validation of the proposed device, it is compared with the simulated results of ATLASTM, a device simulator from SILVACO.

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Investigating short channel effects and performance parameters of double gate junctionless transistor at various technology nodes

2015 2nd International Conference on Recent Advances in Engineering & Computational Sciences (RAECS) ◽

10.1109/raecs.2015.7453429 ◽

2015 ◽

Cited By ~ 3

Author(s):

Vishal Narula ◽

Charu Narula ◽

Jatinder Singh

Keyword(s):

Double Gate ◽

Short Channel Effects ◽

Performance Parameters ◽

Short Channel ◽

Junctionless Transistor ◽

Channel Effects ◽

And Performance ◽

Technology Nodes

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Integration of Solid Phase Epitaxial Re-Growth, Flash and Sub-Melt Laser Annealing for S/D Junctions in CMOS Digital Technology

MRS Proceedings ◽

10.1557/proc-0912-c02-07 ◽

2006 ◽

Vol 912 ◽

Cited By ~ 1

Author(s):

Simone Severi ◽

Emmanuel Augendre ◽

Kristin De Meyer

Keyword(s):

Digital Technology ◽

Laser Annealing ◽

Solid Phase ◽

Significant Gain ◽

Short Channel Effects ◽

Short Channel ◽

Annealing Conditions ◽

Epitaxial Regrowth ◽

Channel Effects ◽

As Solid Phase

AbstractSeveral aspects of the integration of diffusion-less junctions in a NMOS and PMOS conventional flows are evaluated. Processes as Solid Phase Epitaxial Regrowth (SPER) or advanced annealing techniques, as flash or laser, demonstrates benefits not only on the 1D junction profiles but also on the transistor characteristics. An optimization of the implants and of the annealing conditions lead to improved or equivalent transistors performance and short channel effects control compared to the conventional spike RTA process. A significant gain in the overlap capacitance could allow for reduced CV/I. Furthermore the junction leakage can be lowered down to the values reached with the conventional spike RTA process.

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Leakage Current Analysis of 6T & 7T-SRAM using FINFETs at 22nm Technology

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.k2292.1081219 ◽

2019 ◽

Vol 8 (12) ◽

pp. 2983-2986

Keyword(s):

Memory Cell ◽

Leakage Power ◽

Short Channel Effects ◽

Mos Transistors ◽

Current Analysis ◽

Leakage Currents ◽

Short Channel ◽

Channel Effects ◽

Package Density ◽

And Performance

Persistent scaling of planar MOSFET results in increase in transistor package density and performance of chip. However at nanometer regime , it has become a very challenging issue due to the increase in the short channel effects. In nanoscaled MOSFETs, the channel loses control from gate terminal due to potential at drain. Due to this, it is difficult to turn off MOSFET completely which inturn leads to leakage currents. Since cache memory occupies more area of processors, it is difficult to reduce leakage power in microprocessors. Double gate transistors have become replacement for MOS transistors at nano level. Since FINFETs have double gates, the leakage currents can be controlled effectively than planar MOSFET. In this paper, leakage currents of 6T & 7T-SRAM memory cell are analyzed using FINFETs at 22nm technology in hspice software

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