NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed–Muller Network Synthesis Using Parallel Tabular Technique

Proposed work presents an OR-XNOR-based thermal-aware synthesis approach to reduce peak temperature by eliminating local hotspots within a densely packed integrated circuit. Tremendous increase in package density at sub-nanometer technology leads to high power-density that generates high temperature and creates hotspots. A nonexhaustive meta-heuristic algorithm named nondominated sorting genetic algorithm-II (NSGA-II) has been employed for selecting suitable input polarity of mixed polarity dual Reed–Muller (MPDRM) expansion function to reduce the power-density. A parallel tabular technique is used for input polarity conversion from Product-of-Sum (POS) to MPDRM function. Without performance degradation, the proposed MPDRM approach shows more than 50% improvement in the area and power savings and around 6% peak temperature reduction for the MCNC benchmark circuits than that of earlier literature at the logic level. Algorithmic optimized circuit decompositions are implemented in physical design domain using CADENCE INNOVUS and HotSpot tool and silicon area, power consumption and absolute temperature are reported to validate the proposed technique.

Leakage Current Analysis of 6T & 7T-SRAM using FINFETs at 22nm Technology

Persistent scaling of planar MOSFET results in increase in transistor package density and performance of chip. However at nanometer regime , it has become a very challenging issue due to the increase in the short channel effects. In nanoscaled MOSFETs, the channel loses control from gate terminal due to potential at drain. Due to this, it is difficult to turn off MOSFET completely which inturn leads to leakage currents. Since cache memory occupies more area of processors, it is difficult to reduce leakage power in microprocessors. Double gate transistors have become replacement for MOS transistors at nano level. Since FINFETs have double gates, the leakage currents can be controlled effectively than planar MOSFET. In this paper, leakage currents of 6T & 7T-SRAM memory cell are analyzed using FINFETs at 22nm technology in hspice software

Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENTTM Software

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

Nonlinear Power Inductors for Large Current Crest Factors

A practical method is presented: how to adjust the inductance curve of a nonlinear (saturable) inductor with respect to a desired shape. For this purpose, a nonlinear model was developed based on finite element method (FEM). It is shown how a highly efficient construction with low stray fields and maximum package density can be achieved. Different prototype inductors were realized to illustrate the practical capability of photovoltaic (PV) inverters as well as active power factor correction (PFC) applications. All simulations are verified by means of experimental data drawn from electrical measurements.

Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density. The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.

Effect of Dielectric Selection on Sintering Behavior of LTCC

Low Temperature Cofired Ceramic (LTCC) is a versatile ceramic packaging technology. LTCC's functionality and performance can be enhanced with the incorporation of passive devices such as resistors, capacitors, and inductors into the structure of the substrate. This incorporation, which eliminates surface mount solder joints is desirable for improving system reliability and allows for increased package density. Commercially available dielectrics for embedding capacitors into LTCC are limited and the incorporation of such systems into LTCC substrates poses processing challenges related to material compatibility. This paper will review multiple dielectric systems and techniques for embedding capacitors into LTCC as well as present new data related to the cofiring behavior of LTCC and custom dielectrics.

Optimization of thermal distribution in ceramics and LTCC structures applied to sensor elements

Thermal properties of Pt or RuO2 thick‐film heaters made on alumina, aluminum nitride or low temperature co‐fired ceramics (LTCC) were compared in the first step of our work. Special holes to improve the heat distribution were included. Several heater layouts were analysed. The heat distribution was measured by an infrared camera, at different heating power. Second, the optimization of LTCC constructions was carried out. The simple structure of LTCC permitted the achievement of a high package density. It was possible to integrate a heating element made from special thick‐film ink as a buried film, inside a substrate. An important step in our technology was the making of the holes. A pattern of holes (achieved by punching or laser cutting) around the heating area permitted a changeable heat gradient. The quality of lamination and the structure of the buried elements were investigated with an ultrasonic microscope.