Challenges in Integrating the High-K Gate Dielectric Film to the Conventional Cmos Process Flow

ABSTRACTZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.