Properties and Application of Undoped Hydrogenated Microcrystalline Silicon Thin Films

1989 ◽  
Vol 149 ◽  
Author(s):  
J. Kanicki ◽  
E. Hasan ◽  
D. F. Kotecki ◽  
T. Takamori ◽  
J. H. Griffith
Keyword(s):  
Grain Size ◽  
Deposition Temperature ◽  
Etch Rate ◽  
Chemical Vapor ◽  
Microcrystalline Silicon ◽  
Silicon Thin Films ◽  
Hydrogen Dilution ◽  
Average Grain Size ◽  
Structural And Electrical Properties ◽  
Deposition Conditions

ABSTRACTDevice quality undoped hydrogenated microcrystalline silicon has been prepared by plasma enhanced chemical vapor deposition under different conditions. The dependence of physical, chemical, structural, and electrical properties on the deposition conditions has been investigated. Conductive (conductivity above 10−3Ω−1 cm−1) and resistive (conductivity around 10−9Ω−1cm−1) layers having approximately the same grain size, at a given substrate temperature, have been deposited between 200 and 500°C at two different hydrogen dilutions. Independently of the hydrogen dilution, the average grain sized is dependent on the deposition temperature and the film thickness; and a maximum average grain size of about 40 nm has been achieved for a thick film deposited at 500°C. The density of paramagnetic defects also increases with increasing deposition temperature, which indicates that more dangling bond defects are introduced as the total area of the grain boundaries increases. The etch rate decreases with increasing deposition temperature, and for the films deposited at 250 and 500°C the etch rate has been measured to be 6.6 and 2.7 nm/min, respectively. Thin film transistors incorporating a microcrystalline channel have been fabricated and evaluated. The best device had the following properties: field effect mobility, threshold voltage, and on/off current ratio of about 0.8 cm2/V sec, below 5 V, and around 106, respectively.

Properties of High Conductivity Phosphorous Doped Hydrogenated Microcrystalline Silicon and Application in Thin Film Transistor Technology

1989 ◽  
Vol 149 ◽  
Author(s):  
J. Kanicki ◽  
E. Hasan ◽  
J. Griffith ◽  
T. Takamori ◽  
J. C. Tsang
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Thin Film Transistor ◽  
Chemical Vapor ◽  
Effective Field ◽  
Microcrystalline Silicon ◽  
Average Grain Size ◽  
Vapor Deposition Technique ◽  
Structural And Electrical Properties ◽  
Hydrogenated Amorphous

ABSTRACTDevice quality phosphorous (P) doped hydrogenated microcrystalline silicon (n+μc - Si:H) has been prepared by using the plasma enhanced chemical vapor deposition technique. The dependence of physical, chemical, structural and electrical properties on substrate temperature have been investigated. Conductivities for thick films up to 12 Ω−lcm−1 and 40 Ω−1cm−1 have been achieved for layers deposited at 300°C and 500°C, respectively. For films 50 nm thick deposited at 300°C a conductivity of about 5 Ω−1cm−1 has been obtained. A maximum average grain size around 30 nm was obtained. The etch rates of P-doped microcrystalline silicon have been found to be between 8 and 10 times higher than that of undoped hydrogenated amorphous silicon (a-Si:H) films deposited at the same temperature. Thin film transistors incorporating heavily P-doped amorphous and microcrystalline layer between source/drain metal and the a-Si:H channel have been fabricated. We show that an n+μc - Si:H source/drain contacts in thin film transistors provides very good characteristics, yielding an average effective field effect mobility, threshold voltage, and on/off current ratio of about 0.9cm2V−1 sec−1, below 4 V, and above 107, respectively.

Influence of Deposition Temperature on Microcrystalline Silicon Thin Film Prepared by Plasma Enhanced Chemical Vapor Deposition

2011 ◽  
Vol 181-182 ◽  
pp. 401-404
Author(s):  
Lan Li Chen ◽  
Sheng Zhao Wang ◽  
Ying Peng Yin ◽  
Ming Ji Shi
Keyword(s):  
Thin Film ◽  
Grain Size ◽  
Stainless Steel ◽  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Deposition Temperature ◽  
Chemical Vapor ◽  
Microcrystalline Silicon ◽  
Silicon Thin Film ◽  
Experimental Conditions

The influence of deposition temperature (Ts) on glass/stainless steel-based intrinsic amorphous/microcrystalline silicon thin film prepared at different temperature was investigated by PECVD technology. The crystallization ratio and grain size of the silicon thin film at different deposition temperature is studied. The results reveal that the crystallization ratio and grain size of silicon thin film changed along with Ts. The crystallization ratio and grain size of the silicon thin film become larger when Ts=400 °C. On this work, optimal μc-Si:H can be obtained at 400°C deposition temperature in the suitable experimental conditions.

Intrinsic and Doped m c-Si:H TFT Layers using 13.56 MHz PECVD at 250°C

2004 ◽  
Vol 808 ◽  
Author(s):  
Czang-Ho Lee ◽  
Denis Striakhilev ◽  
Arokia Nathan
Keyword(s):  
Performance Improvement ◽  
Volume Fraction ◽  
Chemical Vapor ◽  
Dark Conductivity ◽  
Rf Power ◽  
Crystalline Volume Fraction ◽  
Microcrystalline Silicon ◽  
Bias Stress ◽  
Hydrogen Dilution ◽  
Low Threshold

ABSTRACTUndoped and n+ hydrogenated microcrystalline silicon (μc-Si:H) films for thin film transistors (TFTs) were deposited at a temperature of 250°C with 99 ∼ 99.6 % hydrogen dilution of silane by standard 13.56 MHz plasma enhanced chemical vapor deposition (PECVD). High crystallinity m c-Si:H films were achieved at 99.6 % hydrogen dilution and at low rf power. An undoped 80 nm thick m c-Si:H film showed a dark conductivity of the order of 10−7 S/cm, the photosensitivity of an order of 102, and a crystalline volume fraction of 80 %. However, a 60 nm thick n+ μc-Si:H film deposited using a seed layer showed a high dark conductivity of 35 S/cm and a crystalline volume fraction of 60 %. Using n+ μc-Si:H films as drain and source contact layers in a-Si:H TFTs provides substantial performance improvement over n+ a-Si:H contacts. Finally, fully μ c-Si:H TFTs incorporating intrinsic m c-Si:H films as channel layers and n+ μc-Si:H films as contact layers have been fabricated and characterized. These TFTs exhibit a low threshold voltage and a field effect mobility of 0.85 cm2/Vs, and are far more stable under gate bias stress than a-Si:H TFTs.

Material Reliability of Low-Temperature Boron Deposition for PureB Silicon Photodiode Fabrication

MRS Advances ◽  
2018 ◽  
Vol 3 (57-58) ◽  
pp. 3397-3402 ◽  
Author(s):  
L.K. Nanver ◽  
K. Lyon ◽  
X. Liu ◽  
J. Italiano ◽  
J. Huffman
Keyword(s):  
High Temperature ◽  
Layer Thickness ◽  
Vapor Deposition ◽  
Dark Current ◽  
Deposition Temperature ◽  
Chemical Vapor ◽  
Silicon Photodiode ◽  
In Situ Methods ◽  
Deposition Conditions

ABSTRACTThe chemical-vapor deposition conditions for the growth of pure boron (PureB) layers on silicon at temperatures as low as 400°C were investigated with the purpose of optimizing photodiodes fabricated with PureB anodes for minimal B-layer thickness, low dark current and chemical robustness. The B-deposition is performed in a commercially-available Si epitaxial reactor from a diborane precursor. In-situ methods commonly used to improve the cleanliness of the Si surface before deposition are tested for a deposition temperature of 450°C and PureB layer thickness of 3 nm. Specifically, high-temperature baking in hydrogen, and exposure to HCl are tested. Both material analysis and electrical diode characterization indicate that these extra cleaning steps degrade the properties of the PureB layer and the fabricated diodes.

Stress in Hydrogenated Microcrystalline Silicon Thin Films

1999 ◽  
Vol 557 ◽  
Author(s):  
D. Peiró ◽  
C. Voz ◽  
J. Bertomeu ◽  
J. Andreu ◽  
E. Martínez ◽  
...  
Keyword(s):  
Mechanical Properties ◽  
Vapor Deposition ◽  
Volume Fraction ◽  
Chemical Vapor ◽  
Hot Wire ◽  
X Ray Diffraction ◽  
Microcrystalline Silicon ◽  
X Ray ◽  
Silicon Thin Films ◽  
Abrupt Changes

AbstractHydrogenated microcrystalline silicon films have been obtained by hot-wire chemical vapor deposition (HWCVD) in a silane and hydrogen mixture at low pressure (<5 × 10-2 mbar). The structure of the samples and the residual stress were characterised by X- ray diffraction (XRD). Raman spectroscopy was used to estimate the volume fraction of the crystalline phase, which is in the range of 86 % to 98%. The stress values range between 150 and -140 MPa. The mechanical properties were studied by nanoindentation. Unlike monocrystalline wafers, there is no evidence of abrupt changes in the force-penetration plot, which have been attributed to a pressure-induced phase transition. The hardness was 12.5 GPa for the best samples, which is close to that obtained for silicon wafers.

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