Lateral Uniformity of Ultra-Shallow Junctions Formed by Rapid Thermal Annealing in Polysilicon-on-Silicon Systems

1991 ◽  
Vol 224 ◽  
Author(s):  
S. Batra ◽  
K. Park ◽  
S. Banerjee ◽  
T. Smith ◽  
B. Mulvaney
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Diffusion Front ◽  
Vertical Diffusion ◽  
Transmission Electron ◽  
Shallow Junctions ◽  
Polysilicon Films ◽  
Ultra Shallow Junctions ◽  
Defect Interactions ◽  
Si Films

AbstractLateral non-uniformities can be expected in the dopant diffusion front in the substrate in polysilicon-on-single crystal Si systems upon Rapid Thermal Annealing (RTA), because the grain boundaries in polysilicon act as fast diffusant pipelines and also possibly inject defects into the substrate, which can locally enhance diffusivities in the substrate due to dopant-point defect interactions. The lateral uniformity of As, B and P ultra-shallow junctions formed in the substrate by indiffusion from as-deposited amorphous or polysilicon films has been studied using concentration dependent etching and transmission electron microscopy. Due to a larger final grain size after annealing in the case of as-deposited amorphous Si films compared to asdeposited polysilicon films, there is significant lateral doping inhomogeneities in the diffusion front. However, the doping inhomogeneities are gradually smeared out as the impurities diffuse deeper into the substrate due to lateral as well as vertical diffusion.

Recrystallization of Implanted LPCVD Amorphous Si Films Using Rapid Thermal Annealing

1986 ◽  
Vol 74 ◽  
Author(s):  
R. Kwor ◽  
S. M. Tang ◽  
N. S. Alvi
Keyword(s):  
Electron Microscopy ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Dwell Time ◽  
Hall Effect Measurement ◽  
Temperature Coefficient Of Resistance ◽  
Annealing Conditions ◽  
Transmission Electron ◽  
Amorphous Si ◽  
Si Films

AbstractThe effect of rapid thermal annealing on the crystallization of arsenic and boron implanted amorphous silicon films is studied. Amorphous Si films of 4000 Å were deposited using LPCVD and implanted with arsenic or boron to doses of 5 × 1013, 5 × 1014, and 5 × 1015 cm−2. These films were then annealed using an Eaton Nova-400 RTA system (with temperature ranging from 900 to 1200 °C and dwell time ranging from 1 to 30 sec). The annealed films were studied using transmission electron microscopy, Hall effect measurement and temperature coefficient of resistance measurement. The optimal annealing conditions for the films were found.

Shallow Junction Formation in As-Implanted Si by Low-Temperature Rapid Thermal Annealing

1989 ◽  
Vol 147 ◽  
Author(s):  
M. K. El-Ghor ◽  
S. J. Pennycook ◽  
R. A. Zuhr
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Dislocation Loops ◽  
Cross Sectional ◽  
Dopant Activation ◽  
Transmission Electron ◽  
Shallow Junctions ◽  
Surface Image ◽  
Long Time ◽  
Short Time

AbstractShallow junctions were formed in single-crystal Si(100) by implantation of As at energies between 2 and 17.5 keV followed by conventional furnace annealing or by rapid thermal annealing (RTA). Cross-sectional transmission electron microscopy (XTEM) showed that defect-free shallow junctions could be formed at temperatures as low as 700 °C by RTA, with about 60% dopant activation. From a comparison of short-time and long-time annealing, it is proposed that surface image forces are responsible for the efficient removal of end-of-range (EOR) dislocation loops

RTA-Preparation of β-FeSi2 Layers from MBE-Grown Fe-Si Films Deposited on Si and Relaxed SiGe (100) Substrates

1995 ◽  
Vol 387 ◽  
Author(s):  
M. LíBezný ◽  
J. Poortmans ◽  
J. Dekoster ◽  
S. Degroote ◽  
A. Vantomme ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Microscopy Study ◽  
Electron Microscopy Study ◽  
Structural Defects ◽  
Surfaces And Interfaces ◽  
Transmission Electron ◽  
Current Voltage ◽  
Si Films ◽  
P Type

AbstractRapid thermal annealing (RTA) of Fe-Si layers co-deposited on n- and p- type Si (100) and Si-capped relaxed Si0.6Ge0.4 (100) substrates was studied. Relaxed (100) Si0.6Ge0.4 epitaxial layers represent a pseudo-matched substrate for the β-FeSi2 phase. Fe-Si layers with a 1:2 composition ratio were deposited at room temperature in an MBE system. Samples were then subjected to a rapid thermal annealing in a H2/N2-atmosphere in the temperature range between 500 and 800 °C. Conversion electron Mössbauer spectroscopy showed that the layers consist of the β-FeSi2 phase. Nomarski microscopy revealed crystal grains of the diameter from 5 to 10 μm. Cross-section transmission electron microscopy study found smooth surfaces and interfaces. No significant structural defects were found inside the grains. Differences between current-voltage characteristics of simple devices prepared on these layers agree with the trends expected from their band diagrams.

Ultra-Shallow Junctions by Ion Implantation and Rapid Thermal Annealing: Spike-Anneals, Ramp Rate Effects

1999 ◽  
Vol 568 ◽  
Author(s):  
Aditya Agarwal ◽  
Hans-J. Gossmann ◽  
Anthony T. Fiory
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Driving Forces ◽  
Recent Experimental Data ◽  
Enhanced Diffusion ◽  
Temperature Ramp ◽  
Rate Effects ◽  
Low Energies ◽  
Ultra Shallow Junctions ◽  
P Type

ABSTRACTOver the last couple of years rapid thermal annealing (RTA) equipment suppliers have been aggressively developing lamp-based furnaces capable of achieving ramp-up rates on the order of hundreds of degrees per second. One of the driving forces for adopting such a strategy was the experimental demonstration of 30nm p-type junctions by employing a ramp-up rate of ≈400°C/s. It was subsequently proposed that the ultra-fast temperature ramp-up was suppressing transient enhanced diffusion (TED) of boron which results from the interaction of the implantation damage with the dopant. The capability to achieve very high temperature ramp-rates was thus embraced as an essential requirement of the next generation of RTA equipment.In this paper, recent experimental data examining the effect of the ramp-up rate during spike-and soak-anneals on enhanced diffusion and shallow junction formation is reviewed. The advantage of increasing the ramp-up rate is found to be largest for the shallowest, 0.5-keV, B implants. At such ultra-low energies (ULE) the advantage arises from a reduction of the total thermal budget. Simulations reveal that a point of diminishing return is quickly reached when increasing the ramp-up rate since the ramp-down rate is in practice limited. At energies where TED dominates, a high ramp-up rate is only effective in minimizing diffusion if the implanted dose is sufficiently small so that the TED can be run out during the ramp-up portion of the anneal; for larger doses, a high ramp-up rate only serves to postpone the TED to the ramp-down duration of the anneal. However, even when TED is minimized at higher implant energies via high ramp-up rates, the advantage is unobservable due to the rather large as-implanted depth. It appears then that while spike anneals allow the activation of ULE-implanted dopants to be maximized while minimizing their diffusion the limitation imposed by the ramp-down rate compromises the advantage of very aggressive ramp-up rates.

Rapid Thermal Anneaung of Arsenic-Phosphorus(N+-N-) Double-Diffused Shallow Junctions

1985 ◽  
Vol 52 ◽  
Author(s):  
D. L. Kwong ◽  
N. S. Alvi ◽  
Y. H. Ku ◽  
A. W. Cheung
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Experimental Results ◽  
Silicon Substrates ◽  
Electrical Characteristics ◽  
Shallow Junctions

ABSTRACTDouble-diffused shallow junctions have been formed by ion implantation of both phosphorus and arsenic ions into silicon substrates and rapid thermal annealing. Experimental results on defect removal, impurity activation and redistribution, effects of Si preamorphization, and electrical characteristics of Ti-silicided junctions are presented.

Observation of the Wurtzite Phase in OMVPE Grown ZnSe/GaAs: Effect on Implantation and Rapid Thermal Annealing

1989 ◽  
Vol 147 ◽  
Author(s):  
K. S. Jones ◽  
J. Yu ◽  
P. D. Lowen ◽  
D. Kisker
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Electrical Transport ◽  
High Resistivity ◽  
Ion Milling ◽  
Electrical Transport Properties ◽  
Wurtzite Phase ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Diffraction Patterns

AbstractTransmission electron diffraction patterns of cross-sectional TEM samples of OMVPE ZnSe on GaAs indicate the existence of the hexagonal wurtzite phase in the epitaxial layers. The orientation relationship is (0002)//(111); (1120)//(220). Etching studies indicate the phase is internal not ion milling induced. The average wurtzite particle size is 80Å-120Å. Because of interplanar spacing matches it is easily overlooked. Electrical property measurements show a high resistivity (1010ω/square) which drops by four orders of magnitude upon rapid thermal annealing between 700°C and 900 °C for 3 sec. Implantation of Li and N have little effect on the electrical transport properties. The Li is shown to have a high diffusivity, a solid solubility of ≈1016/cm3 at 800°C and getters to the ZnSeA/aAs interface.

Influence of the Rapid Thermal Annealing on the Properties of Thin a-Si Films

2004 ◽  
Vol 455-456 ◽  
pp. 108-111
Author(s):  
N. Nedev ◽  
G. Beshkov ◽  
Elvira Fortunato ◽  
S.S. Georgiev ◽  
T. Ivanov ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Si Films

Novel resistance reduction and phase changes of contacts to n-type InP by rapid thermal annealing

2002 ◽  
Vol 744 ◽  
Author(s):  
J.S. Huang ◽  
T. Nguyen ◽  
N. Bar-Chaim ◽  
C.B. Vartuli ◽  
S. Anderson ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Thermal Annealing ◽  
Interfacial Reaction ◽  
Rapid Thermal Annealing ◽  
Phase Changes ◽  
Long Wavelength ◽  
Transmission Electron ◽  
Resistance Reduction ◽  
Scanning Transmission ◽  
Metallic Compounds

ABSTRACTWe studied the influence of n-metal alloy on the long wavelength InP device performance. Various alloy schemes of rapid thermal annealing (RTA) were experimented to obtain the optimized contact resistance for the n-InP/AuGe/Ni/Au/Cr/Au metallization systems. Significant resistance reduction was achieved at 390°C for 45sec with wafer flattening step at 310°C. Using scanning transmission electron microscopy (STEM) and Auger electron spectroscopy (AES) analyses, we showed that resistance was correlated with interfacial reaction at the n-InP/metal. For the high resistance devices, little interfacial reaction between n-InP and Au occurred. For the low resistance devices, significant out-diffusion of P in the bottom Au and Ni layers occurred, forming Au-P and Ni-P metallic compounds. In addition, accumulation of Ge in the Ni layer was also detected. We suggest that Ni-P is very critical in obtaining low contact resistance for n-InP.

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