Dopant Redistribution in Titanium Silicide/n+ Polysilicon Bilayers During Rapid Thermal Processing

1983 ◽  
Vol 23 ◽  
Author(s):  
C. B. Cooper ◽  
R. A. Powell ◽  
R. Chow
Keyword(s):  
Sheet Resistance ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Blackbody Radiation ◽  
Titanium Silicide ◽  
Sputter Deposited ◽  
Short Annealing ◽  
Dopant Redistribution ◽  
Phosphorus Doped ◽  
Isothermal Mode

ABSTRACTThe successful use of rapid thermal processing in an isothermal mode to form Ti polycide structures is described. The silicide was sputter deposited from a composite Ti-Si target onto phosphorus-doped poly-Si. The resulting polycide structure was annealed by exposure to the blackbody radiation from a resistively-heated graphite heater. Rapid diffusion of the P into the Ti silicide is observed even for short annealing times, although resulting P concentrations in the silicide (>7 × 1018cm−3) are relatively low, about 100 times lower than in the doped poly-Si. Properly chosen RTP parameters can minimize the sheet resistance of the polycide without increasing the sheet resistance of the underlying poly-Si layer, which has not been possible for furnace-annealed samples.

A parametric study of titanium silicide formation by rapid thermal processing

1996 ◽  
Vol 11 (2) ◽  
pp. 412-421 ◽  
Author(s):  
A. V. Amorsolo ◽  
P. D. Funkenbusch ◽  
A. M. Kadin
Keyword(s):  
Sheet Resistance ◽  
Parametric Study ◽  
Thermal Processing ◽  
Annealing Temperature ◽  
Rapid Thermal Processing ◽  
Titanium Silicide ◽  
Wet Etching ◽  
Silicide Formation ◽  
Temperature Variations ◽  
Sputter Etching

A parametric study of titanium silicide formation by rapid thermal processing was conducted to determine the effects of annealing temperature (650 °C, 750 °C), annealing time (30 s, 60 s), wet etching (no HF dip, with HF dip), sputter etching (no sputter etch, with sputter etch), and annealing ambient (Ar, N2) on the completeness of conversion of 60 nm Ti on (111)-Si to C54–TiSi2 based on sheet resistance and the uniformity of the sheet resistance measurements across the entire wafer. Statistical analysis of the results showed that temperature, annealing ambient, and sputter etching had the greatest influence. Increasing the temperature and using argon gas instead of nitrogen promoted conversion of the film to C54–TiSi2. On the other hand, sputter etching retarded it. The results also indicated significant interactions among these factors. The best uniformity in sheet resistance was obtained by annealing at 750 °C without sputter etching. The different sheet resistance profiles showed gradients that were consistent with expected profile behaviors, arising from temperature variations across the wafer due to the effect of a flowing cold gas and the effects of the wafer edge and flats.

The Effects of Processing Ambient on the Reaction Rate of Ti and Si Using Rapid Thermal Processing

1986 ◽  
Vol 74 ◽  
Author(s):  
A. Kermani ◽  
K. Farnam ◽  
T. Stultz
Keyword(s):  
Thin Layer ◽  
Thermal Processing ◽  
Reaction Rate ◽  
Sintering Temperature ◽  
Rapid Thermal Processing ◽  
Titanium Silicide ◽  
The Self ◽  
Silicide Film ◽  
Sputter Deposited ◽  
Ti Films

AbstractThe reaction rate of sputter deposited Ti films on c-Si as a function of process ambient was studied. Sintering temperatures ranging from 600 to 1100° C, under pure ammonia, forming gas, nitrogen and argon were used. The additional effect of a reactively sputtered TiN cap on the reaction rate was also investigated. Processed films were then analyzed using AES, RBS and four point probe resistivity mapping. It was found that for temperatures below 700° C, an ammonia ambient has the most pronounced effect on reducing the rate of formation of titanium silicide, followed by forming gas (N 2/H2 10% vol), nitrogen and argon. Additionally, the presence of the TiN cap further reduced the reaction rate while exhibiting significant diffusion of nitrogen into the silicide film. For the samples annealed in ambients containing nitrogen, a thin layer of Tix Ny was simultaneously formed on top of the silicide film. The thickness and Stoichiometry of this titanium nitride films were then correlated with the sintering temperature and ambient. The details of these findings and their impact on the formation of the self-aligned titanium silicide (salicide) will be presented.

The Effect of Lamps Radius on Thermal Stresses for Rapid Thermal Processing System

2003 ◽  
Vol 125 (3) ◽  
pp. 504-511 ◽  
Author(s):  
Ching-Kong Chao ◽  
Shih-Yu Hung ◽  
Cheng-Ching Yu
Keyword(s):  
Thermal Processing ◽  
Thermal Stresses ◽  
Maximum Shear Stress ◽  
Rapid Thermal Processing ◽  
Processing System ◽  
Practical Consideration ◽  
Fully Implicit ◽  
Control Scheme ◽  
Potential Applications ◽  
Dopant Redistribution

The concept of rapid thermal processing has many potential applications in microelectronics manufacturing, but the details of chamber design remains an active area of research. In this work the influence of lamps radius on the thermal stresses in a wafer during the cooling process is studied in detail. Since the equations governing the present thermal-elastic system are coupled in nature, the solution for the temperature and stresses must proceed simultaneously by using a fully implicit finite difference method. After the thermal stresses are obtained, the optimum lamps radii for various heights of the chamber under the constant power ramp-down control scheme are determined based on the maximum shear stress failure criterion. The shortest cooling time that can significantly reduce the thermal budget and dopant redistribution is also predicted by applying the maximum stress control scheme. The result obtained is useful in the design of a reliable rapid thermal processor based on a more practical consideration, thermal stress.

Rapid Thermal Annealing and Oxidation of Silicon Wafers with Back-Side Films

1997 ◽  
Vol 470 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Thermal Oxidation ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Temperature Control ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Back Side ◽  
Control Accuracy

ABSTRACTTemperatures for lamp-heated rapid thermal processing of wafers with various back-side films were controlled by a Lucent Technologies pyrometer which uses a/c lamp ripple to compensate for emissivity. Process temperatures for anneals of arsenic and boron implants were inferred from post-anneal sheet resistance, and for rapid thermal oxidation, from oxide thickness. Results imply temperature control accuracy of 12°C to 17°C at 3 standard deviations.

Formation of titanium silicide films by rapid thermal processing

1983 ◽  
Vol 4 (10) ◽  
pp. 380-382 ◽  
Author(s):  
R.A. Powell ◽  
R. Chow ◽  
C. Thridandam ◽  
R.T. Fulks ◽  
I.A. Blech ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Titanium Silicide

Titanium silicide/p-Si Schottky barriers formed by rapid thermal processing in nitrogen

1991 ◽  
Vol 34 (8) ◽  
pp. 827-834 ◽  
Author(s):  
W. De Bosscher ◽  
R.L. Van Meirhaeghe ◽  
W.H. Laflère ◽  
F. Cardon
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Schottky Barriers ◽  
Titanium Silicide

Modeling of Device Characteristics as Function of Ti Salicide Rapid Thermal Processing Parameters for Deep-Sub-Micron CMOS Technologies

1996 ◽  
Vol 429 ◽  
Author(s):  
J. A. Kittl ◽  
D. A. Prinslow ◽  
G. Misium ◽  
M. F. Pas
Keyword(s):  
Sheet Resistance ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing Parameters ◽  
Deep Submicron ◽  
Process Window ◽  
Nucleation Density ◽  
Formation Temperature ◽  
High Temperature Short Time ◽  
Anneal Temperature

AbstractRapid thermal processing is widely applied in self-aligned Ti silicide processes for deep-submicron devices. We investigated and modeled the effects of rapid thermal processing variables (silicide formation temperature and time, and anneal temperature and time) and Ti thickness on deep-sub-micron device characteristics. The effect of Ti thickness, formation temperature and time on diode leakage and bridging due to silicide lateral growth, and its correlation to silicide thickness was analyzed; as well as the effects of these and the anneal variables on n+ gate sheet resistance, silicide to source/drain contact resistance and transistor source-drain series resistance. An expression for n+ gate sheet resistance is given, as function of anneal temperature and time, silicide thickness, linewidth and TiSi2 C49 grain size after formation, based on a nucleation density model in agreement with measurements of TiSi2 C49 to C54 transformation kinetics. The tradeoffs and process window limits are discussed, as well as trends observed when scaling down lateral and vertical dimensions. We show that for advanced technologies, the scaling of silicide thickness and linewidth narrows the process window between full C49 to C54 transformation and agglomeration temperatures. Due to the high activation energy of the C49 to C54 transformation, a process window for low sheet resistance exists only for high temperature-short time processes.

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