Characteristics of Silicon Photodetector Using Epitaxial Wafer with High Resistivity and Long Recombination Lifetime

ABSTRACTFor the high quality Si Photodetector, the high resistivity epitaxial wafer using the low resistivity substrate were studied. The buffer layer was introduced in the interface, and it was very effective on the crystal quality of the epitaxial layer. Recombination lifetime in the epitaxial layer became very uniform and long even in the interface region which was confirmed by measuring the lifetime depth profiles. Then Si PIN Photodiode was fabricated on the above high quality epitaxial wafer and its optoelectric characteristics was evaluated.

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Analysis of GaN-based HEMTS with AlN buffer layers by using Raman spectroscopy

Modern Physics Letters B ◽

10.1142/s0217984921410104 ◽

2021 ◽

pp. 2141010

Author(s):

Cheng Che Lee ◽

Hsin Jung Lee ◽

Hsin Che Lee ◽

Wei Yu Lee ◽

Wei Ching Chuang

Keyword(s):

Raman Spectroscopy ◽

Buffer Layer ◽

Epitaxial Layer ◽

Drain Current ◽

Buffer Layers ◽

Crystal Quality ◽

Subthreshold Slope ◽

Gan Hemts ◽

Aln Buffer

In this paper, AlGaN/GaN HEMTs with an AlN buffer layer were fabricated. Analyses on the crystal quality of the GaN epitaxial layer by Raman spectroscopy have been purposed. By introducing an AlN layer on sapphire substrate, the maximum drain current of the HEMT increased from 481 mA/mm to 522 mA/mm at [Formula: see text] V. Subthreshold slope was reduced from 638.3 mV/decade to 240.9 mV/decade and the electron mobility increased from 1109 cm2 V[Formula: see text]s[Formula: see text] to 1781 cm2 V[Formula: see text]s[Formula: see text]. These results showed that using an AlN buffer layer can improve the crystal quality of the GaN epitaxial layer, thus optimize the device performances of the GaN-based HEMTs.

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Study of the Growth and Dislocation Blocking Mechanisms in InxGa1−xAs Buffer Layer for Growing High-Quality In0.5Ga0.5P, In0.3Ga0.7As, and In0.52Ga0.48As on Misoriented GaAs Substrate for Inverted Metamorphic Multijunction Solar Cell Application

Energy Harvesting and Systems ◽

10.1515/ehs-2014-0006 ◽

2014 ◽

Vol 1 (3-4) ◽

Cited By ~ 1

Author(s):

H. Q. Nguyen ◽

H. W. Yu ◽

C. H. Hsu ◽

V. T. H. Phan ◽

E. Y. Chang

Keyword(s):

Solar Cell ◽

Buffer Layer ◽

Gaas Substrate ◽

Growth Conditions ◽

Crystal Quality ◽

High Quality ◽

Solar Cell Application ◽

Blocking Mechanisms ◽

Multijunction Solar Cell

AbstractEffects of growth conditions and buffer structures on crystal quality of 1.9-eV In

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Investigation of the Heteroepitaxial Process Optimization of Ge Layers on Si (001) by RPCVD

Nanomaterials ◽

10.3390/nano11040928 ◽

2021 ◽

Vol 11 (4) ◽

pp. 928

Author(s):

Yong Du ◽

Zhenzhen Kong ◽

Muhammet Toprak ◽

Guilei Wang ◽

Yuanhao Miao ◽

...

Keyword(s):

High Temperature ◽

Buffer Layer ◽

Layer Thickness ◽

Growth Temperature ◽

Crystalline Quality ◽

Initial Growth ◽

Two Dimensional ◽

High Quality ◽

Reduced Pressure

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski–Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it’s threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm−2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.

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Improvement in crystal quality of ZnO film on Si substrate by using a homo-buffer layer

Materials Science in Semiconductor Processing ◽

10.1016/j.mssp.2009.12.003 ◽

2009 ◽

Vol 12 (6) ◽

pp. 233-237 ◽

Cited By ~ 3

Author(s):

Jie Zhao ◽

Lizhong Hu

Keyword(s):

Buffer Layer ◽

Crystal Quality ◽

Zno Film ◽

Si Substrate

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Growth of 4H-SiC Epitaxial Layer through Optimization of Buffer Layer

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.84 ◽

2018 ◽

Vol 924 ◽

pp. 84-87 ◽

Cited By ~ 3

Author(s):

Nicolò Piluso ◽

Andrea Severino ◽

Ruggero Anzalone ◽

Maria Ausilia di Stefano ◽

Enzo Fontana ◽

...

Keyword(s):

Buffer Layer ◽

Leakage Current ◽

Breakdown Voltage ◽

Epitaxial Layer ◽

Electrical Parameters ◽

Crystallographic Defects

In this work the deposition of buffer layer has been studied in order to increase the quality of the epitaxial layer and improve the performance of device. The comparison between two different thicknesses of buffer layer reveals a decrease of crystallographic defects and an improvement of electrical parameters of MOSFET device as leakage current and breakdown voltage.

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Improvement of the crystalline quality of the ZnO epitaxial layer on a low-temperature grown ZnO buffer layer

Journal of Crystal Growth ◽

10.1016/j.jcrysgro.2004.02.111 ◽

2004 ◽

Vol 266 (4) ◽

pp. 505-510 ◽

Cited By ~ 48

Author(s):

J.F. Yan ◽

Y.M. Lu ◽

Y.C. Liu ◽

H.W. Liang ◽

B.H. Li ◽

...

Keyword(s):

Low Temperature ◽

Buffer Layer ◽

Epitaxial Layer ◽

Crystalline Quality ◽

Zno Buffer Layer

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Improvement in the crystal quality of non-polar a-plane GaN directly grown on an SiO2 stripe-patterned r-plane sapphire substrate

CrystEngComm ◽

10.1039/c9ce00995g ◽

2019 ◽

Vol 21 (34) ◽

pp. 5124-5128 ◽

Cited By ~ 1

Author(s):

Shen Yan ◽

Junhui Die ◽

Caiwei Wang ◽

Xiaotao Hu ◽

Ziguang Ma ◽

...

Keyword(s):

Sapphire Substrate ◽

Crystal Quality ◽

High Quality ◽

Patterned Sapphire Substrate ◽

Direct Growth

In this work, high-quality a-plane GaN was obtained by direct growth on a stripe-patterned sapphire substrate.

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High Quality 4H-SiC Epitaxial Layer by Tuning CVD Process

Materials Science Forum ◽

10.4028/www.scientific.net/msf.963.91 ◽

2019 ◽

Vol 963 ◽

pp. 91-96

Author(s):

Nicolò Piluso ◽

Alberto Campione ◽

Simona Lorenti ◽

Andrea Severino ◽

Giuseppe Arena ◽

...

Keyword(s):

Growth Rate ◽

Buffer Layer ◽

Epitaxial Layer ◽

Defect Density ◽

Strong Dependence ◽

Stacking Faults ◽

Layer Growth ◽

Electrical Performance ◽

Process Time ◽

High Quality

In this work many steps concerning the epitaxial layer growth on 4H-SiC are studied, evaluated and optimized to obtain high quality 4H-SiC epitaxy. The processes evaluated have been studied on a Hot Wall CVD reactor. The first step related to the substrate surface etching has been tuned by choosing the H2 flow, temperature and process time at which most of defects (mainly stacking faults) are not propagated. Then, the buffer layer step has been optimized by increasing the thickness at which an effective reduction of defect density and an improved electrical performance of power devices have been detected. Also, during the buffer layer growth a strong dependence between basal plane dislocations propagation and the growth rate has been observed. A crucial step carefully studied has been the drift layer growth. It was optimized by increasing the growth rate (13<GR<15µm/h) that results in a lower defectiveness, good thickness and doping uniformity. Final stage concerning the cooling of the process has been strongly revisited. A significant decreasing of the morphological defects (carrots, pits) and stacking faults has been observed by slowing the cool down process (~ 25 °C/min).

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