Growth of GaN Thin Films on Sapphire Substrate by Low Pressure MOCVD

1997 ◽  
Vol 468 ◽  
Author(s):  
M. Ishida ◽  
T. Hashimoto ◽  
T. Takayama ◽  
O. Imafuji ◽  
M. Yuri ◽  
...  
Keyword(s):  
High Temperature ◽  
Dislocation Density ◽  
Surface Morphology ◽  
Buffer Layer ◽  
Layer Thickness ◽  
Low Pressure ◽  
Buffer Layers ◽  
Nitridation Time ◽  
Low Pressure Mocvd ◽  
Buffer Layer Thickness

ABSTRACTHigh quality GaN films are grown on sapphire(0001) substrates by low pressure MOCVD using TMG and NH3 as source materials. Effects of surface nitridation and buffer layer thickness on the quality of over-grown GaN films are investigated. It is revealed by atomic force microscope (AFM) observations that surface roughness of the annealed buffer layers strongly depends on the nitridation time. Dislocation density and surface morphology of the high temperature GaN layer depend on the buffer layer thickness. It is found that sufficient surface nitridation of sapphire makes the buffer layer just prior to the high temperature growth very smooth, which is essential to obtain flat thick-GaN on it. It is also found that thickness of the buffer layer largely influences the dislocation density in the over-grown thick GaN. In order to obtain good surface morphology and low dislocation density at the same time, both nitridation time and buffer layer thickness must be optimized.

Effects of ZnO buffer layer thickness on properties of ZnO thin films deposited by low-pressure MOCVD

2004 ◽  
Vol 262 (1-4) ◽  
pp. 456-460 ◽  
Author(s):  
Yuantao Zhang ◽  
Guotong Du ◽  
Boyang Liu ◽  
HuiChao Zhu ◽  
Tianpeng Yang ◽  
...  
Keyword(s):  
Thin Films ◽  
Buffer Layer ◽  
Layer Thickness ◽  
Low Pressure ◽  
Zno Thin Films ◽  
Low Pressure Mocvd ◽  
Buffer Layer Thickness ◽  
Zno Buffer Layer

Effects of AlN buffer layer thickness on the crystallinity and surface morphology of 10-µm-thicka-plane AlN films grown onr-plane sapphire substrates

2016 ◽  
Vol 9 (8) ◽  
pp. 081001 ◽  
Author(s):  
Chia-Hung Lin ◽  
Shinya Tamaki ◽  
Yasuhiro Yamashita ◽  
Hideto Miyake ◽  
Kazumasa Hiramatsu
Keyword(s):  
Surface Morphology ◽  
Buffer Layer ◽  
Layer Thickness ◽  
Sapphire Substrates ◽  
Buffer Layer Thickness ◽  
Aln Buffer

Constraint Effects on Cohesive Failures in Low-k Dielectric Thin Films

2005 ◽  
Vol 863 ◽  
Author(s):  
Ting Y. Tsui ◽  
Andrew J. McKerrow ◽  
Joost J. Vlassak
Keyword(s):  
Thin Films ◽  
Residual Stress ◽  
Buffer Layer ◽  
Layer Thickness ◽  
Silicon Substrate ◽  
Buffer Layers ◽  
Cohesive Failure ◽  
Lag Model ◽  
Buffer Layer Thickness ◽  
Cds Film

AbstractOne of the most common forms of cohesive failure observed in brittle thin films subjected to a tensile residual stress is channel cracking, a fracture mode in which through-film cracks propagate in the film. The crack growth rate depends on intrinsic film properties, residual stress, the presence of reactive species in the environment, and the precise film stack. In this paper, we investigate the effect of various buffer layers sandwiched between a brittle carbon-doped-silicate (CDS) film and a silicon substrate on channel cracking of the CDS film. The results show that channel cracking is enhanced if the buffer layer is more compliant than the silicon substrate. Crack velocity increases with increasing buffer layer thickness and decreasing buffer layer stiffness. This is caused by a reduction of the constraint imposed by the substrate on the film and a commensurate increase in energy release rate. The degree of constraint is characterized experimentally as a function of buffer layer thickness and stiffness, and compared to the results of a simple shear lag model that was proposed previously.

Correlation Between the AlN Buffer Layer Thickness and the GaN Polarity in GaN/AlN/Si(111) Grown by MBE

2002 ◽  
Vol 743 ◽  
Author(s):  
A. M. Sanchez ◽  
P. Ruterana ◽  
P. Vennegues ◽  
F. Semond ◽  
F. J. Pacheco ◽  
...  
Keyword(s):  
Low Temperature ◽  
Buffer Layer ◽  
Layer Thickness ◽  
Buffer Layers ◽  
Nucleation Layer ◽  
Buffer Layer Thickness ◽  
Aln Buffer

ABSTRACTIn this work it is shown that thin AlN buffer layers cause N-polarity GaN epilayers, with a high inversion domains density. When the AlN thickness increases, the polarity of the epilayer changes to Ga. The use of a low temperature AlN nucleation layer leads to a flat AlN/Si(111) interface. This contributes to decrease the inversion domains density in the overgrown GaN epilayer with a Ga polarity.

Fabrication and characterization of metal-ferroelectric-insulator-Si diodes and transistors with different HfSiON buffer layer thickness

2008 ◽  
Vol 23 (10) ◽  
pp. 2727-2732 ◽  
Author(s):  
Xubing Lu ◽  
Hiroshi Ishiwara ◽  
Kenji Maruyama
Keyword(s):  
Electrical Properties ◽  
Buffer Layer ◽  
Layer Thickness ◽  
Leakage Current ◽  
Drain Current ◽  
Memory Window ◽  
Buffer Layers ◽  
Window Width ◽  
Buffer Layer Thickness ◽  
The Impact

Metal-ferroelectric-insulator-Si (MFIS) structures using HfSiON as buffer layers were fabricated, and the impact of buffer layer thickness on the electrical properties of the MFIS devices was investigated. HfSiON films with thickness ranging from 1 to 4 nm were deposited by electron beam evaporation, which exhibited much reduced leakage current when compared to that of SiO2 with the same equivalent oxide thickness. From the viewpoint of polarization and charge injection, the flatband voltage and memory window width dependent on the sweeping voltages were discussed for the MFIS diodes with 1-, 2-, and 4-nm-thick HfSiON buffer layers. Small leakage current as well as excellent long-term data retention characteristics were found for all of these samples. It was also found that MFIS diodes with 2-nm-thick HfSiON buffer layer have the largest memory window width. Ferroelectric-gate transistors fabricated with a Pt/SBT(300nm)/HfSiON (2 nm)/Si gate structure showed a memory window of 0.8 V and a high drain current on/off ratio of 108 for the gate voltage sweep between +4 and −4 V. All of these excellent electrical properties proved that HfSiON acts as an excellent barrier for suppressing both leakage current and atomic interdiffusion.

scholarly journals Micro-Tubular Solid Oxide Fuel Cell Polarization and Impedance Variation With Thin Porous Samarium-Doped Ceria and Gadolinium-Doped Ceria Buffer Layer Thickness

2020 ◽  
Vol 18 (2) ◽  
Author(s):  
Ryan J. Milcarek ◽  
Jeongmin Ahn
Keyword(s):  
Buffer Layer ◽  
Layer Thickness ◽  
Electrochemical Impedance ◽  
Cell Polarization ◽  
Solid Oxide ◽  
Buffer Layers ◽  
Doped Ceria ◽  
Oxide Fuel ◽  
Buffer Layer Thickness ◽  
Gadolinium Doped Ceria

Abstract Porous buffer layers for anode-supported solid oxide fuel cells (SOFCs) have been investigated for many years with different thicknesses of the buffer layer in each study. In this work, micro-tubular SOFCs having samarium-doped ceria (SDC) and gadolinium-doped ceria (GDC) buffer layers are compared using the current–voltage technique, electrochemical impedance spectroscopy, scanning electron microscopy, and energy-dispersive X-ray spectroscopy. The thickness of the porous SDC and GDC buffer layer is investigated systematically with the thickness varying between 0.3 and 2.0 μm. The power density varies between 212 and 1004 mW/cm2 for samples having different SDC buffer layer thickness. Comparable changes occur for the SOFCs with a GDC buffer layer, but less variation in polarization losses resulted. Variation in electrochemical performance varies due to changes in ohmic resistance, cathode activation polarization, and interfacial reactions between the cathode and electrolyte materials.

scholarly journals Non-Toxic Buffer Layers in Flexible Cu(In,Ga)Se2Photovoltaic Cell Applications with Optimized Absorber Thickness

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Md. Asaduzzaman ◽  
Md. Billal Hosen ◽  
Md. Karamot Ali ◽  
Ali Newaz Bahar
Keyword(s):  
Buffer Layer ◽  
Layer Thickness ◽  
Energy Conversion Efficiency ◽  
Absorber Layer ◽  
Buffer Layers ◽  
Reference Type ◽  
Buffer Layer Thickness ◽  
Simulation Results ◽  
Zno Buffer Layer ◽  
Better Than

Absorber layer thickness gradient in Cu(In1−xGax)Se2(CIGS) based solar cells and several substitutes for typical cadmium sulfide (CdS) buffer layers, such as ZnS, ZnO, ZnS(O,OH), Zn1−xSnxOy(ZTO), ZnSe, and In2S3, have been analyzed by a device emulation program and tool (ADEPT 2.1) to determine optimum efficiency. As a reference type, the CIGS cell with CdS buffer provides a theoretical efficiency of 23.23% when the optimum absorber layer thickness was determined as 1.6 μm. It is also observed that this highly efficient CIGS cell would have an absorber layer thickness between 1 μm and 2 μm whereas the optimum buffer layer thickness would be within the range of 0.04–0.06 μm. Among all the cells with various buffer layers, the best energy conversion efficiency of 24.62% has been achieved for the ZnO buffer layer based cell. The simulation results with ZnS and ZnO based buffer layer materials instead of using CdS indicate that the cell performance would be better than that of the CdS buffer layer based cell. Although the cells with ZnS(O,OH), ZTO, ZnSe, and In2S3buffer layers provide slightly lower efficiencies than that of the CdS buffer based cell, the use of these materials would not be deleterious for the environment because of their non-carcinogenic and non-toxic nature.

scholarly journals Investigation of the Heteroepitaxial Process Optimization of Ge Layers on Si (001) by RPCVD

Nanomaterials ◽  
2021 ◽  
Vol 11 (4) ◽  
pp. 928
Author(s):  
Yong Du ◽  
Zhenzhen Kong ◽  
Muhammet Toprak ◽  
Guilei Wang ◽  
Yuanhao Miao ◽  
...  
Keyword(s):  
High Temperature ◽  
Buffer Layer ◽  
Layer Thickness ◽  
Growth Temperature ◽  
Crystalline Quality ◽  
Initial Growth ◽  
Two Dimensional ◽  
High Quality ◽  
Reduced Pressure

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski–Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it’s threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm−2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.

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