Impact of Electrodes on Gate Oxide Reliability: Examples from Isolation and Gate-Stack Processing

1997 ◽  
Vol 473 ◽  
Author(s):  
D. L. Chapek ◽  
K. F. Schuegraf ◽  
R. P. S. Thakur
Keyword(s):  
Integrated Circuits ◽  
Bottom Electrode ◽  
Gate Oxide ◽  
Review Of Literature ◽  
Gate Stack ◽  
Oxide Reliability ◽  
Dielectric System ◽  
Thin Oxide ◽  
The Impact

ABSTRACTThis paper discusses the challenges involved in improving gate oxide reliability for advanced integrated circuits through review of literature and other relevant data. We believe that gate oxide reliability improvements can be engineered by paying special attention to the process conditioning of the top and bottom electrode components of the thin oxide dielectric system in advanced ULSI technologies. We present examples that demonstrate the impact of process and materials on the performance of thin oxide. The data encompasses the effects of substrate, isolation, and top electrodes on gate oxide quality using a variety of methodologies to assess reliability.

The impact of F contamination induced by the process on the gate oxide reliability

1998 ◽  
Vol 38 (2) ◽  
pp. 255-258 ◽  
Author(s):  
G Ghidini ◽  
C Clementi ◽  
D Drera ◽  
F Maugain
Keyword(s):  
Gate Oxide ◽  
Oxide Reliability ◽  
The Impact

Effect of Phosphorus-Doped Polysilicon Anneal on Thin Oxide Reliability as Probed with X-Ray Damage Characterization

1994 ◽  
Vol 338 ◽  
Author(s):  
R. Nachman ◽  
F. Cerrina
Keyword(s):  
Gate Oxide ◽  
Radiation Sensitivity ◽  
Oxide Charge ◽  
X Ray ◽  
Damage Characterization ◽  
Oxide Reliability ◽  
The Creation ◽  
Thin Oxide ◽  
Phosphorus Doped ◽  
Mos Structures

ABSTRACTIn this paper we address the degradation of oxide reliability after annealing the phosphorusdoped polysilicon of MOS structures. The oxide reliability was studied in terms of X-ray radiation sensitivity as well as breakdown characteristics.We found that annealing the polysilicon increased the radiation sensitivity of the gate oxide. We believe that this increase is a result of the phosphorus out-diffusion from the polysilicon into the oxide and a result of the creation of phosphorus related traps in the oxide bulk. We also found that the oxide charge to breakdown (Qbd) degradation correlates well with the density of the phosphorus in the oxide.

Effect of Poly-Si on Electromigration Behaviors and Microstructure Characteristics of Au Metallization

1998 ◽  
Vol 516 ◽  
Author(s):  
T. Lee ◽  
B.R. York ◽  
B. Lindgren ◽  
H. Kentzinger ◽  
J. Lee ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Line Length ◽  
Current Gain ◽  
X Ray Diffraction ◽  
X Ray ◽  
Microstructure Characteristics ◽  
Oxide Reliability ◽  
Thermal Oxide ◽  
The Impact ◽  
Dc Stress

AbstractFor BJT and MOSFET, poly-Si is the most critical layer used as an emitter to improve the current gain in BJT and as a gate to improve the gate oxide reliability in MOSFET. In both cases, the poly-Si is then connected to the conductor. It is very important to understand how poly-Si affects the microstructure and the electromigration behavior of conductor. NIST test structures (length = 800μ, thickness = 0.7μ, widths = 1, 5, 10 μ) with Au conductor and TiW/TiWN/TiW barrier were used to study the impact of poly-Si. Two groups of samples were used: one with poly-Si under the barrier and the other without poly-Si. Thermal oxide was used to isolate the substrate from the conductor and Si3N4, was used as passivation. DC stress was performed at 175, 200, and 225°C. Microbeam X-ray Diffraction (μ XRD) was used to characterize the microstructure of the TiW barrier and Au metallization layers as a function of line length and width. The data indicates that samples with poly-Si have lower electromigration resistance for Au conductors for all widths and temperatures, with higher initial deformation fault densities on poly-Si.

The Impact of Deuterated CMOS Processing on Gate Oxide Reliability

2005 ◽  
Vol 52 (9) ◽  
pp. 2111-2115 ◽  
Author(s):  
A.J. Hof ◽  
E. Hoekstra ◽  
A.Y. Kovalgin ◽  
R. vanSchaijk ◽  
W.M. Baks ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Oxide Reliability ◽  
The Impact ◽  
Cmos Processing

Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate

1998 ◽  
Author(s):  
Ching-Lang Chiang ◽  
Neeraj Khurana ◽  
Daniel T. Hurley ◽  
Ken Teasdale
Keyword(s):  
Integrated Circuits ◽  
Ccd Camera ◽  
Preparation Technique ◽  
Absorption Data ◽  
Ir Radiation ◽  
Heavily Doped ◽  
Emission Microscopy ◽  
Diffraction Patterns ◽  
Emission Detection ◽  
The Impact

Abstract Backside emission microscopy on heavily doped substrate materials was analyzed from the viewpoint of optical absorption by the substrate and sample preparation technique. Although it was widely believed that silicon is transparent to infrared (IR) radiation, we demonstrated by using published absorption data that silicon with doping levels above 5 x 1018cm-3 is virtually opaque, leaving only a narrow transmission window around the energy bandgap. Because the transmission depends exponentially on the thickness of die, thinning to below 100µm is shown to be required. Even an advanced IR sensor such as HgCdTe would find little light to detect without thinning the die. For imaging the circuit, an IR laser-based system produced poor images in which the diffraction patterns often ruined the contrast and obscured the image. Hence, a precise, controlled die thinning technique is required both for emission detection and backside imaging. A thinning and polishing technique was briefly described that was believed to be applicable to most ceramic packages. A software technique was employed to solve the image quality problem commonly encountered in backside imaging applications using traditional microscope light source and a scientific grade CCD camera. Finally, we showed the impact of die thickness on imaging circuits on a heavily doped n type substrate.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

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