The impact of F contamination induced by the process on the gate oxide reliability

1998 ◽  
Vol 38 (2) ◽  
pp. 255-258 ◽  
Author(s):  
G Ghidini ◽  
C Clementi ◽  
D Drera ◽  
F Maugain
1997 ◽  
Vol 473 ◽  
Author(s):  
D. L. Chapek ◽  
K. F. Schuegraf ◽  
R. P. S. Thakur

ABSTRACTThis paper discusses the challenges involved in improving gate oxide reliability for advanced integrated circuits through review of literature and other relevant data. We believe that gate oxide reliability improvements can be engineered by paying special attention to the process conditioning of the top and bottom electrode components of the thin oxide dielectric system in advanced ULSI technologies. We present examples that demonstrate the impact of process and materials on the performance of thin oxide. The data encompasses the effects of substrate, isolation, and top electrodes on gate oxide quality using a variety of methodologies to assess reliability.


1998 ◽  
Vol 516 ◽  
Author(s):  
T. Lee ◽  
B.R. York ◽  
B. Lindgren ◽  
H. Kentzinger ◽  
J. Lee ◽  
...  

AbstractFor BJT and MOSFET, poly-Si is the most critical layer used as an emitter to improve the current gain in BJT and as a gate to improve the gate oxide reliability in MOSFET. In both cases, the poly-Si is then connected to the conductor. It is very important to understand how poly-Si affects the microstructure and the electromigration behavior of conductor. NIST test structures (length = 800μ, thickness = 0.7μ, widths = 1, 5, 10 μ) with Au conductor and TiW/TiWN/TiW barrier were used to study the impact of poly-Si. Two groups of samples were used: one with poly-Si under the barrier and the other without poly-Si. Thermal oxide was used to isolate the substrate from the conductor and Si3N4, was used as passivation. DC stress was performed at 175, 200, and 225°C. Microbeam X-ray Diffraction (μ XRD) was used to characterize the microstructure of the TiW barrier and Au metallization layers as a function of line length and width. The data indicates that samples with poly-Si have lower electromigration resistance for Au conductors for all widths and temperatures, with higher initial deformation fault densities on poly-Si.


2005 ◽  
Vol 52 (9) ◽  
pp. 2111-2115 ◽  
Author(s):  
A.J. Hof ◽  
E. Hoekstra ◽  
A.Y. Kovalgin ◽  
R. vanSchaijk ◽  
W.M. Baks ◽  
...  

1995 ◽  
Vol 35 (3) ◽  
pp. 603-608 ◽  
Author(s):  
S.R. Anderson ◽  
R.D. Schrimpf ◽  
K.F. Galloway ◽  
J.L. Titus

2001 ◽  
Vol 664 ◽  
Author(s):  
C. Y. Wang ◽  
E. H. Lim ◽  
H. Liu ◽  
J. L. Sudijono ◽  
T. C. Ang ◽  
...  

ABSTRACTIn this paper the impact of the ESL (Etch Stop layer) nitride on the device performance especially the threshold voltage (Vt) has been studied. From SIMS analysis, it is found that different nitride gives different H concentration, [H] in the Gate oxide area, the higher [H] in the nitride film, the higher H in the Gate Oxide area and the lower the threshold voltage. It is also found that using TiSi instead of CoSi can help to stop the H from diffusing into Gate Oxide/channel area, resulting in a smaller threshold voltage drift for the device employed TiSi. Study to control the [H] in the nitride film is also carried out. In this paper, RBS, HFS and FTIR are used to analyze the composition changes of the SiN films prepared using Plasma enhanced Chemical Vapor deposition (PECVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) with different process parameters. Gas flow ratio, RF power and temperature are found to be the key factors that affect the composition and the H concentration in the film. It is found that the nearer the SiN composition to stoichiometric Si3N4, the lower the [H] in SiN film because there is no excess silicon or nitrogen to be bonded with H. However the lowest [H] in the SiN film is limited by temperature. The higher the process temperature the lower the [H] can be obtained in the SiN film and the nearer the composition to stoichiometric Si3N4.


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