Deposition of Highly Conductive n+ Silicon Film for a-Si:H Thin Film Transistor

1998 ◽  
Vol 507 ◽  
Author(s):  
Yue Kuo ◽  
K. Latzko
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Silicon Film ◽  
Chemical Vapor ◽  
Channel Length ◽  
Process Conditions ◽  
Silicon Thin Film ◽  
Wide Range ◽  
Phosphorus Doped ◽  
Deposited Films

ABSTRACTPlasma enhanced chemical vapor deposition of phosphorus-doped n+ silicon film over a wide range of process conditions has been studied. The deposited films were characterized with SIMS, Raman, and XRD. An unusually abrupt change of resistivity over a small SiH4(1% PH3) flow rate has been observed and was correlated to the variation of the film's morphology from amorphous to micrycrystalline. The grains are less than 50 Å in size and has strong <111> orientation. Amorphous silicon thin film transistors with microcrystalline n+ source and drain contacts have consistently good device characteristics. However, the contact resistance is comparable to the channel resistance when the channel length approaches 1 micrometer.

A New Model for Series Resistance of Amorphous Silicon Thin Film Transistor

1992 ◽  
Vol 258 ◽  
Author(s):  
Yong S. Kim ◽  
Jin S. Park ◽  
Seong K. Lee ◽  
Jung R. Hwang ◽  
Hong S. Choi ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Series Resistance ◽  
Operating Temperature ◽  
Thin Film Transistor ◽  
Channel Length ◽  
Silicon Thin Film ◽  
Short Channel ◽  
New Model ◽  
Wide Range

ABSTRACTWe presents a new model for the series resistance of an amorphous silicon (a-Si) thin film transistor (TFT) with an inverted-staggered configuration, considering the current spreading under the source and the drain contacts as well as the space charge limited current. The calculated results of our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the relative contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which has been verified successfully by the experimental measurements.

Switch-On Transients And Static Characteristics Of Polymorphous And Amorphous Silicon Thin-Film Transistor

2003 ◽  
Vol 762 ◽  
Author(s):  
V. Tripathi ◽  
Y. N. Mohapatra
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Amorphous Silicon ◽  
Thin Film Transistor ◽  
Chemical Vapor ◽  
Localized States ◽  
Silicon Thin Film ◽  
Hydrogen Dilution ◽  
Order Of Magnitude ◽  
Switching Characteristics

AbstractHydrogenated polymorphous silicon (Pm-Si:H) being an admixture of amorphous and ordered phase silicon shows improved optical and electrical properties due to the presence of nanocrystallites. In order to compare the dynamic and steady state electrical properties in a-Si:H and pm-Si:H, bottom gate Thin Film Transistors (TFT) of these materials were fabricated with SiO2 as the insulating layer. The active materials were deposited using plasma-enhanced chemical vapor deposition (PECVD) by varying pressure, temperature and hydrogen dilution. Transfer characteristics of TFTs made using pm-Si:H show lower leakage current, higher on-current and sharper volt per decade change as compared to similar TFTs made from a-Si:H. Density of states in pm-Si:H as calculated from field effect conductance using incremental method is observed to be an order of magnitude lower than in a-Si:H based devices. To compare dynamic characteristics, we studied the switch-on transient characteristics of polymorphous and amorphous silicon TFTs by pulsing the gate to different voltages in the temperature range of 150-300K. The switch-on transients are trap limited with overall better switching characteristics for pm-Si:H samples. An initial rising transient in case of pm-Si:H is activated with an effective energy of 0.3 eV. The origins of transients are interpreted in terms of trap limited carrier dynamics and charge redistribution within the distribution of localized states.

Self-Aligned Nanocrystalline Silicon Thin-Film Transistor With Deposited n+ Source/Drain Layer

2007 ◽  
Vol 989 ◽  
Author(s):  
I-Chun Cheng ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Chemical Vapor ◽  
Nanocrystalline Silicon ◽  
The Self ◽  
Silicon Thin Film ◽  
Plastic Substrates ◽  
N Source ◽  
Lift Off ◽  
Made In

AbstractWe demonstrated self-aligned nanocrystalline silicon (nc-Si:H) n-channel thin film transistors (TFTs) with directly deposited n+ layer. The silicon layers were deposited by plasma-enhanced chemical vapor deposition at a substrate temperature of 150°C. The TFTs were made in a staggered top-gate, bottom-source/drain geometry with a seed layer underneath. The self-alignment of top-gate to the bottom-source/drain was achieved by backside exposure photolithography through the glass substrate and the silicon layers, followed by a lift-off process. An extent of gate to source/drain overlap of 1.5 mm was obtained. The self-aligned TFTs have similar characteristics to their non-self-aligned counterpart. This result represents an important step toward directly deposited nc-Si:H TFT backplanes on plastic substrates.

Exploration of Amorphous Silicon Thin Film Transistor Degradation with Thermal Anneal

1993 ◽  
Vol 297 ◽  
Author(s):  
R.F. Kwasnick ◽  
G.E. Possin ◽  
W.L. Hill II
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Substrate Surface ◽  
Thin Film Transistor ◽  
Transfer Characteristic ◽  
Channel Length ◽  
Silicon Thin Film ◽  
Short Channel ◽  
Effective Mobility ◽  
Long Channel

We have measured the device characterisics of short and long channel inverted- staggered hydrogenated amorphous silicon thin film transistors (TFTs) with either Mo or Cr source/drain metal after annealing at temperatures from 225 C to 275 C. The TFT deposition temperature at the substrate surface was about 270 C. From the slope of the transfer characteristic an effective mobility is extracted. Devices with Mo source/drain metal exhibit an initial effective mobility increase at short times (within about 30 min), while those with Cr do not. At long times the mobility of all devices decreases. The mobility changes are greatest for short channel length devices because of contact effects. The channel length dependence of the behavior permits a separation of the device behavior into contact and intrinsic mobility components.

Contact Effects in High Mobility Microcrystalline Silicon Thin-Film Transistors

2007 ◽  
Vol 989 ◽  
Author(s):  
Kah Yoong Chan ◽  
Eerke Bunte ◽  
Helmut Stiebig ◽  
Dietmar Knipp
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
High Mobility ◽  
Chemical Vapor ◽  
Channel Length ◽  
Microcrystalline Silicon ◽  
Silicon Thin Film ◽  
Short Channel ◽  
Long Channel

AbstractMicrocrystalline silicon (mc-Si:H) has recently been proven to be a promising material for thin-film transistors (TFTs). We present mc-Si:H TFTs fabricated by plasma-enhanced chemical vapor deposition at temperatures below 200°C in a condition similar to the fabrication of amorphous silicon TFTs. The mc-Si:H TFTs exhibit device mobilities exceeding 30 cm2/Vs and threshold voltages in the range of 2.5V. Such high mobilities are observed for long channel devices (50-200 mm). For short channel device (2 mm), the mobility reduces to 7 cm2/Vs. Furthermore the threshold voltage of the TFTs decreases with decreasing channel length. A simple model is developed, which explains the observed reduction of the device mobility and threshold voltage with decreasing channel length by the influence of drain and source contacts.

A New Device Model of Amorphous Silicon Thin-Film Transistor for Circuit Simulation

1991 ◽  
Vol 219 ◽  
Author(s):  
Hong S. Choi ◽  
Jin S. Park ◽  
Chang H. Oh ◽  
In S. Joo ◽  
Yong S. Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Analytical Model ◽  
Circuit Simulation ◽  
Thin Film Transistor ◽  
Drain Current ◽  
Channel Length ◽  
Silicon Thin Film ◽  
New Device ◽  
Circuit Simulator

ABSTRACTWe present a new analytical model of amorphous silicon thin-film transistor (a-Si TFT) suitable for circuit simulators such as SPICE. The effects of localized gap state distributions of a-Si as well as temperatures on the a-Si TFT performances have been fully considered in the presented model. The parameters used in SPICE, such as transconductance, channel-length modulation, and power factor of source-drain current, are evaluated from the measured current-voltage and capacitance-voltage characteristics by employing the proposed extraction method. It has been found out that the analytical model is in good agreement with experimental data at both room temperature and elevated temperature and successfully implemented in a widely used circuit simulator.

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