Smart-Cut® Technology: an Industrial Application of Ion Implantation Induced Cavities

1998 ◽  
Vol 510 ◽  
Author(s):  
B. Aspar ◽  
C. Lagahe ◽  
H. Moriceau ◽  
A. Soubie ◽  
M. Bruel ◽  
...  

AbstractThe Smart-Cut® process is based on proton implantation and wafer bonding. Proton implantation enables delamination of a thin layer from a thick substrate to be achieved whereas the wafer bonding technique enables different multilayer structures to be achieved by transferring the delaminated layer onto a second substrate. One of the best known applications of Smart Cut® is the Silicon On Insulator structure. The physical mechanisms involved in the delamination process are discussed based on the study of Proton-induced microcavity formation during implantation and growth during annealing. The experimental results on the time and temperature required to achieve delamination lead to different activation energies depending on the implantation conditions and resistivity of the substrate. All the experiments indicate that growth of microcavities is mainly controlled by hydrogen diffusion. The growth of these microcavities and the pressure inside them induce delamination when the catastrophic radius of the microcavities is reached.

1992 ◽  
Vol 262 ◽  
Author(s):  
Akira Usami ◽  
Taichi Natori ◽  
Akira Ito ◽  
Shun-ichiro Ishigami ◽  
Yutaka Tokuda ◽  
...  

ABSTRACTSilicon-on-insulator films fabricated by the wafer bonding technique were studied with capacitance-voltage (c-V) and deep-level transient spectroscopy (DLTS) measurements. For our experiments, two kinds of SOI wafers were prepared. Many voids were present in one sample (void sample), but few voids were in the other sample (no void sample). Before annealing, two DLTS peaks (E-0.48 eV and Ec-0.38 eV) were observed in the SOI layer of the void sample. For the no void sample, different two DLTS peaks (Ec-0.16 eV and Ec-0.12 eV) were observed. The trap with an activation energy of 0.48 eV was annealed out after 450 °C annealing for 24 h. On the other hand, other traps were annealed out after 450 °C annealing for several hours. During annealing at 450 °C, thermal donors (TDs) were formed simultaneously. In usual CZ sil icon, a DLTS peak of TD was observed around 60 K. In the no void sample, however, a TD peak was observed at a temperature lower than 30 K. This TD was annihilated by rapid thermal annealing. This suggests that the TD with a shallower level was formed in the no void sample after annealing at 450 °C.


1991 ◽  
Vol 220 ◽  
Author(s):  
D. Godbey ◽  
L. Palkuti ◽  
P. Leonov ◽  
A. Krist ◽  
J. Wang ◽  
...  

ABSTRACTUndoped thin layer silicon on insulator has been fabricated using wafer bonding and selective etching techniques using an MBE grown Si0.7Ge0.3 layer as an etch stop. Defect free, undoped 200–350 nm silicon layers are routinely fabricated using this procedure. A new selective silicon-germanium etch has been developed that significantly improves the ease of fabrication of the BESOI material.


2000 ◽  
Vol 39 (Part 1, No. 4B) ◽  
pp. 2435-2438
Author(s):  
Satoshi Kodama ◽  
Tomofumi Furuta ◽  
Noriyuki Watanabe ◽  
Hiroshi Ito ◽  
Atsushi Kanda ◽  
...  

1990 ◽  
Vol 29 (Part 2, No. 12) ◽  
pp. L2311-L2314 ◽  
Author(s):  
Takao Abe ◽  
Tokio Takei ◽  
Atsuo Uchiyama ◽  
Katsuo Yoshizawa ◽  
Yasuaki Nakazato

2001 ◽  
Vol 227-228 ◽  
pp. 906-910 ◽  
Author(s):  
K. Dessein ◽  
P.S. Anil Kumar ◽  
S. Németh ◽  
L. Delaey ◽  
G. Borghs ◽  
...  

2004 ◽  
Vol 58 (3-4) ◽  
pp. 465-469
Author(s):  
Xinyun Xie ◽  
Qing Lin ◽  
Weili Liu ◽  
Chenglu Lin

2012 ◽  
Vol 195 ◽  
pp. 75-78
Author(s):  
Chung Kyung Jung ◽  
Sung Wook Joo ◽  
Seoung Hun Jeong ◽  
Sang Wook Ryu ◽  
Han Choon Lee ◽  
...  

Over the last decades, the concept of backside illumination (BSI) sensors has become one of the leading solutions to optical challenges such as improved quantum efficiency (QE), and cross-talk, respectively [1-. Direct wafer bonding is a method for fabricating advanced substrates for micro-electrochemical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer.


2012 ◽  
Vol 2012 (CICMT) ◽  
pp. 000436-000440 ◽  
Author(s):  
S. Günschmann ◽  
M. Fischer ◽  
T. Bley ◽  
I. Käpplinger ◽  
W. Brode ◽  
...  

For the fabrication of a micro fluidic high pressure oil sensor (400 bar) based on an infrared transmission measuring principle the bonding of 2 mm silicon wafers is necessary. Conventional bonding techniques such as silicon fusion bonding or anodic bonding are not suitable for bonding thick and inflexible silicon wafers, because these techniques can not compensate for the wafer bow. We present a new bonding procedure for silicon substrates thicker than 1 mm using a silicon adapted LTCC tape as an intermediate leveling layer. The wafers are preprocessed by etching a nano structured silicon surface on the internal side. The silicon wafers are aligned and stacked with pre-structured green LTCC tapes by an optical stacking unit. During the hot isostatic lamination at 55 bar the structured LTCC tape is adjusted to the silicon. A subsequent pressure assisted sintering leads to a wafer bonding strength up to 5000 N/cm2. With the bonding technique it is possible to create cavities and channels between the thick wafers by the use of punched and laser cut LTCC. The fabrication steps of the sandwich build-up especially the sequential lamination and the optical adjusting procedure of the flexible (LTCC) and inflexible (2 mm Wafer) substrates will be explained in detail. A method to reduce the shrinkage and distortion of the green LTCC during handling is demonstrated. The distribution of the bonding and bursting strength of the single fluidic systems on a complete sandwich substrate is analyzed.


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