Bonding of 2 mm thick silicon wafers using LTCC as an intermediate layer

2012 ◽  
Vol 2012 (CICMT) ◽  
pp. 000436-000440 ◽  
Author(s):  
S. Günschmann ◽  
M. Fischer ◽  
T. Bley ◽  
I. Käpplinger ◽  
W. Brode ◽  
...  

For the fabrication of a micro fluidic high pressure oil sensor (400 bar) based on an infrared transmission measuring principle the bonding of 2 mm silicon wafers is necessary. Conventional bonding techniques such as silicon fusion bonding or anodic bonding are not suitable for bonding thick and inflexible silicon wafers, because these techniques can not compensate for the wafer bow. We present a new bonding procedure for silicon substrates thicker than 1 mm using a silicon adapted LTCC tape as an intermediate leveling layer. The wafers are preprocessed by etching a nano structured silicon surface on the internal side. The silicon wafers are aligned and stacked with pre-structured green LTCC tapes by an optical stacking unit. During the hot isostatic lamination at 55 bar the structured LTCC tape is adjusted to the silicon. A subsequent pressure assisted sintering leads to a wafer bonding strength up to 5000 N/cm2. With the bonding technique it is possible to create cavities and channels between the thick wafers by the use of punched and laser cut LTCC. The fabrication steps of the sandwich build-up especially the sequential lamination and the optical adjusting procedure of the flexible (LTCC) and inflexible (2 mm Wafer) substrates will be explained in detail. A method to reduce the shrinkage and distortion of the green LTCC during handling is demonstrated. The distribution of the bonding and bursting strength of the single fluidic systems on a complete sandwich substrate is analyzed.

Author(s):  
Peter Pegler ◽  
N. David Theodore ◽  
Ming Pan

High-pressure oxidation of silicon (HIPOX) is one of various techniques used for electrical-isolation of semiconductor-devices on silicon substrates. Other techniques have included local-oxidation of silicon (LOCOS), poly-buffered LOCOS, deep-trench isolation and separation of silicon by implanted oxygen (SIMOX). Reliable use of HIPOX for device-isolation requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of HIPOX-related stresses in the structures is of interest because structuraldefects, if formed, could electrically degrade devices.This investigation was performed to study the origin and behavior of defects in recessed HIPOX (RHIPOX) structures. The structures were exposed to a boron implant. Samples consisted of (i) RHlPOX'ed strip exposed to a boron implant, (ii) recessed strip prior to HIPOX, but exposed to a boron implant, (iii) test-pad prior to HIPOX, (iv) HIPOX'ed region away from R-HIPOX edge. Cross-section TEM specimens were prepared in the <110> substrate-geometry.


2000 ◽  
Vol 39 (Part 1, No. 4B) ◽  
pp. 2435-2438
Author(s):  
Satoshi Kodama ◽  
Tomofumi Furuta ◽  
Noriyuki Watanabe ◽  
Hiroshi Ito ◽  
Atsushi Kanda ◽  
...  

2015 ◽  
Vol 107 (26) ◽  
pp. 261107 ◽  
Author(s):  
Zihao Wang ◽  
Ruizhe Yao ◽  
Stefan F. Preble ◽  
Chi-Sen Lee ◽  
Luke F. Lester ◽  
...  

2001 ◽  
Vol 227-228 ◽  
pp. 906-910 ◽  
Author(s):  
K. Dessein ◽  
P.S. Anil Kumar ◽  
S. Németh ◽  
L. Delaey ◽  
G. Borghs ◽  
...  

2019 ◽  
Vol 89 (6) ◽  
pp. 952
Author(s):  
Р.К. Яфаров

AbstractVariations of the morphology and field-emission properties of surface-structured n - and p -type silicon wafers have been studied. The silicon surface has been structured by etching in a fluorine–carbon plasma and depositing subnanodimensional island carbon masks. It has been shown that surface structuring in a fluorine–carbon plasma makes it possible to reach desired field-emission currents in electric fields of different strengths. Physicochemical models of field emission mechanisms and models of destruction of surface-modified multipoint silicon array cathodes have been considered.


2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001221-001252 ◽  
Author(s):  
Kei Murayama ◽  
Mitsuhiro Aizawa ◽  
Mitsutoshi Higashi

The bonding technique for High density Flip Chip(F.C.) packages requires a low temperature and a low stress process to have high reliability of the micro joining ,especially that for sensor MEMS packages requires hermetic sealing so as to ensure their performance. The Transient Liquid Phase (TLP) bonding, that is a kind of diffusion bonding is a technique that connects the low melting point material such as Indium to the higher melting point metal such as Gold by the isothermal solidification and high-melting-point intermetallic compounds are formed. Therefore, it is a unique joining technique that can achieve not only the low temperature bonding and also the high temperature reliability. The Gold-Indium TLP bonding technique can join parts at 180 degree C and after bonding the melting point of the junction is shifted to more than 495 degree C, therefore itfs possible to apply the low temperature bonding lower than the general use as a lead free material such as a SAC and raise the melting point more than AuSn solder which is used for the high temperature reliability usage. Therefore, the heat stress caused by bonding process can be expected to be lowered. We examined wafer bonding and F.C bonding plus annealing technique by using electroplated Indium and Gold as a joint material. We confirmed that the shear strength obtained at the F.C. bonding plus anneal technique was equal with that of the wafer bonding process. Moreover, it was confirmed to ensure sufficient hermetic sealing in silicon cavity packages that had been bonded at 180 degree C. And the difference of the thermal stress that affect to the device by the bonding process was confirmed. In this paper, we report on various possible application of the TLP bonding.


Sign in / Sign up

Export Citation Format

Share Document