Modeling Soft Breakdown of Ultra-Thin Gate Oxide Layers

1999 ◽  
Vol 567 ◽  
Author(s):  
Michel Houssa ◽  
P.W. Mertens ◽  
M.M. Heyns
Keyword(s):  
Gate Voltage ◽  
Dielectric Breakdown ◽  
Percolation Cluster ◽  
Gate Oxide ◽  
Oxide Layers ◽  
Long Range Correlations ◽  
Electrical Stress ◽  
Non Gaussian ◽  
Thin Gate Oxide ◽  
Soft Breakdown

ABSTRACTThe time-dependent dielectric breakdown of MOS capacitors with ultra-thin gate oxide layers is investigated. After the occurrence of soft breakdown, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. It is shown that this behavior can be explained by assuming that a percolation path is formed between the electron traps generated in the gate oxide layer during electrical stress of the capacitors. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian as well as that long-range correlations exist in the system after soft breakdown. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of charges within the percolation cluster formed at soft breakdown.

High Temperature Gate Voltage Step-by-Step Test to Assess Reliability Differences in 1200 V SiC MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 1033-1044
Author(s):  
Elena Mengotti ◽  
Enea Bianda ◽  
Stephan Wirths ◽  
David Baumann ◽  
Jason Bettega ◽  
...  
Keyword(s):  
Gate Voltage ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Imperfect Interface ◽  
Step Test ◽  
Limiting Factor ◽  
Voltage Step ◽  
Good Reliability ◽  
Time Dependent Dielectric Breakdown ◽  
Thin Gate Oxide

In this paper, robustness and reliability differences related to the performance of the gate oxide of commercially-available 1200 V-rated planar and trench SiC MOSFETs have been investigated. Due to a thin gate oxide in SiC MOSFETs and to a naturally imperfect interface of the oxide layer (SiO2) with the SiC material, its quality and reliability become very important and could be a limiting factor of the SiC technology when compared to the Si one. A dedicated gate oxide step-by-step (VG SbS) tester has been prepared during which the gate voltage is varied with different profiles. Results of Fowler-Nordheim (FN), Time Dependent Dielectric Breakdown (TDDB) and three test runs of the VG SbS are presented in this paper. Both technologies show good reliability figures to allow the use in the application. Trench technology shows higher robustness limits whereas the extrapolated reliability at the rated gate voltage is superior for the planar one.

Soft breakdown of ultra-thin gate oxide layers

1996 ◽  
Vol 43 (9) ◽  
pp. 1499-1504 ◽  
Author(s):  
M. Depas ◽  
T. Nigam ◽  
M.M. Heyns
Keyword(s):  
Gate Oxide ◽  
Oxide Layers ◽  
Thin Gate Oxide ◽  
Soft Breakdown

Triggering and Suppression of Soft Breakdown During Mercury-Probe Assessment of Thin Gate Oxide Quality

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Evseev ◽  
A. Cacciato
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Oxide Layers ◽  
Current Stress ◽  
Thin Gate Oxide ◽  
Soft Breakdown ◽  
Microelectronic Manufacturing ◽  
Routine Assessment ◽  
Probe Measurements ◽  
Gate Oxide Integrity

ABSTRACTThe breakdown of ultra-thin gate oxide layers is investigated using fast-feedback Hg-probe measurements to perform Exponentially Ramped Current Stress (ERCS) tests. Several parameters have been varied in the ERCS test: oxide thickness (4nm, 5nm, 6nm and 7nm), capacitor area (0.12cm2 and 0.023cm2) and initial injected current (5×10−5 A and 5×10−4 A). Soft breakdown is detected only in case of oxides thinner than 5 nm. It is found that the fraction of points on the wafer on which soft breakdown occurs reduces by increasing the value of the injected current at the beginning of the ERCS test or completely disappears by decreasing the capacitor area. Consequences of current results for correct routine assessment of gate oxide integrity in microelectronic manufacturing are discussed.

scholarly journals Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs

2007 ◽  
Vol 84 (9-10) ◽  
pp. 2081-2084 ◽  
Author(s):  
J.M. Rafí ◽  
E. Simoen ◽  
A. Mercha ◽  
K. Hayama ◽  
F. Campabadal ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Electrical Stress ◽  
Thin Gate Oxide

Single Event Gate Rupture in SiC MOS Capacitors with Different Gate Oxide Thicknesses

2014 ◽  
Vol 778-780 ◽  
pp. 440-443 ◽  
Author(s):  
Manato Deki ◽  
Takahiro Makino ◽  
Kazutoshi Kojima ◽  
Takuro Tomita ◽  
Takeshi Ohshima
Keyword(s):  
Dielectric Breakdown ◽  
Ion Irradiation ◽  
Gate Oxide ◽  
Heavy Ion ◽  
Single Event ◽  
Leakage Currents ◽  
Mos Capacitors ◽  
Heavy Ion Irradiation ◽  
Mos Devices ◽  
Thin Gate Oxide

The leakage currents through the gate oxide of MOS capacitors fabricated on n-type 4H-Silicon Carbide (SiC) was measured under accumulation bias conditions with heavy-ion irradiation. The Linear Energy Transfer (LET) dependence of the critical electric field (Ecr) at which dielectric breakdown occurred in these capacitors with two different oxide thicknesses was evaluated. The MOS capacitors with thin gate oxide showed higherEcrvalues than those with thick gate oxide. The linear relationship between the reciprocalEcrandLETwas observed for both MOS capacitors. The slope ofLETdependence of 1/Ecrfor SiC MOS capacitors was smaller than that for Si, suggesting that SiC MOS devices are less susceptible to single-event gate rupture (SEGR) than Si MOS devices.

Effects of Silicon Ion Implantation upon Thin Gate Oxide Integrity

1992 ◽  
Vol 262 ◽  
Author(s):  
G. -S. Lee ◽  
J. -G. Park ◽  
S. -P. Choi ◽  
C. -H. Shin ◽  
Y. -B. Sun ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Surface Region ◽  
Gate Oxide ◽  
Near Surface ◽  
Time Dependent Dielectric Breakdown ◽  
Thin Gate Oxide ◽  
Si Ion Implantation ◽  
Gate Oxide Integrity

ABSTRACTIn this study, using oxide breakdown voltage and time-dependent-dielectric breakdown measurements, thermal wave modulated reflectance and chemical etching/optical microscopy, we investigated effects of Si ion implantation upon formation of D-defects and thin gate oxide integrity. Our data show that addition of Si ion implantation with a dose of up to 1013 ions/cm2 improves oxide integrity if the implantation is done at a certain step just before sacrificial oxidation in the Mb DRAM process. However, no improvement in oxide integrity is observed when the same implantation is done on the virgin wafer surfaces at the start of the same Mb DRAM process. We discuss our hypothesis that the improvement in oxide integrity is due to a reduction in the D-defect density in the near-surface region of the wafer.

Hot-carrier degradation for 90 nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

2007 ◽  
Vol 16 (3) ◽  
pp. 821-825
Author(s):  
Chen Hai-Feng ◽  
Hao Yue ◽  
Ma Xiao-Hua ◽  
Li Kang ◽  
Ni Jin-Yu
Keyword(s):  
Gate Voltage ◽  
Gate Oxide ◽  
Gate Length ◽  
Hot Carrier ◽  
Voltage Stress ◽  
Thin Gate Oxide ◽  
Hot Carrier Degradation

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

2015 ◽  
Vol 821-823 ◽  
pp. 753-756 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Martin Rambach ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Inert Gas ◽  
Breakdown Field ◽  
Wafer Surface ◽  
Mos Devices ◽  
Uniform Current ◽  
Thin Gate Oxide ◽  
Mos Structures

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Performance of Poly-Si Tfts with Double Gate Oxide Layers

1996 ◽  
Vol 424 ◽  
Author(s):  
Byung-Hyuk Min ◽  
Cheol-Min Park ◽  
Jae-Hong Jun ◽  
Byung-Sung Bae ◽  
Min-Koo Han
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Insulator ◽  
Double Gate ◽  
Electrical Parameters ◽  
Electrical Field ◽  
Oxide Layers ◽  
Oxide Breakdown ◽  
Electrical Stress ◽  
Low Threshold

AbstractWe have fabricated a poly-Si TFT with double gate insulator composed of ECR oxide and APCVD oxide to improved the performance of poly-Si TFTs. The poly-Si TFT with double gate oxide exhibits the remarkable enhancement of the electrical parameters compared with the conventional poly-Si TFTs which has APCVD gate oxide, such as improvement of the subthreshold swing and the low threshold voltage. The proposed poly-Si TFT has a higher oxide breakdown electrical field and the device characteristics are not degraded significantly after an electrical stress. It is found that the ECR oxide plays a key role to improve the device performances and prevent the poly-Si TFTs from degradation due to the electrical stress.

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