Nucleation-Control and Enhancement of Solid-Phase-Crystallization of SiGe-Heterostructure

2000 ◽  
Vol 638 ◽  
Author(s):  
S. Yamaguchi ◽  
S. K. Park ◽  
N. Sugii

AbstractThe crystallization of SiGe-heterostructure in which a thin Ge layer put between Si layers has been investigated. When the Ge layer is inside the Si layer, the crystallization phenomena are similar to those of SiGe alloy layer; Ge completely diffuses in Si layer during the crystallization. When the Ge layer is at the interface between the Si layer and the quartz substrate, significant enhancement of crystallization has been found. In this structure, decrease in surface free-energy increases the nucleation rate at the interface and causes anomalous localization of Ge at the interface. When the Ge layer is on the surface of the Si layer, the crystallization property is quite different from the other structures. The underlying Si layer has large and aligned grains when the furnace annealing is assisted by the laser-annealing.A part of this work was carried out under the ASET program supported by NEDO, Japan.

1983 ◽  
Vol 23 ◽  
Author(s):  
T. P. Smith ◽  
P. J. Stiles ◽  
W. M. Augustyniak ◽  
W. L. Brown ◽  
D. C. Jacobson ◽  
...  

ABSTRACTFormation of buried insulating layers and redistribution of impurities during annealing are important processes in new semiconductor device technologies. We have studied pulsed ruby laser and furnace annealing of high dose (D>1017 N/cm2) 50 KeV nitrogen implanted silicon. Using He Back scattering and channeling, X-ray diffraction, transmission electron microscopy, and infrared transmission spectroscopy, we have compared liquid and solid phase regrowth, diffusion, impurity segregation and nitride formation. As has been previously reported, during furnace annealing at or above 1200C nitrogen redistributes and forms a polycrystalline silicon nitride (Si3N4 ) layer. [1–4] In contrast, pulsed laser annealing produces a buried amorphous silicon nitride layer filled with voids or bubbles below a layer of polycrystalline silicon.


1990 ◽  
Vol 182 ◽  
Author(s):  
Ichio Yudasaka ◽  
Hiroyuki Ohshima

AbstractPolysilicon thin film transistors are now in mass production. Key factors of the success are thinner polysilicon film and thermal oxidation. Practical applications of polysilicon thin film transistors have been limited, however, because of high temperature processing. Alternative technologies to thermal oxidation are very low pressure deposition, solid-phase crystallization, laser-annealing and hydrogenation. These technologies are compatible with low temperature processing and will contribute to the advance of polysilicon thin film transistors in the future.


1996 ◽  
Vol 424 ◽  
Author(s):  
Reece Kingi ◽  
Yaozu Wang ◽  
Stephen J. Fonash ◽  
Osama Awadelkarim ◽  
John Mehlhaff

AbstractRapid thermal annealing and furnace annealing for the solid phase crystallization of amorphous silicon thin films deposited using PECVD from argon diluted silane have been compared. Results reveal that the crystallization time, the growth time, and the transient time are temperature activated, and that the resulting polycrystalline silicon grain size is inversely proportional to the annealing temperature, for both furnace annealing and rapid thermal annealing. In addition, rapid thermal annealing was found to result in a lower transient time, a lower growth time, a lower crystallization time, and smaller grain sizes than furnace annealing, for a given annealing temperature. Interestingly, the transient time, growth time, and crystallization time activation energies are much lower for rapid thermal annealing, compared to furnace annealing.We propose two models to explain the observed differences between rapid thermal annealing and furnace annealing.


2010 ◽  
Vol 44-47 ◽  
pp. 4154-4156
Author(s):  
Rui Min Jin ◽  
Ding Zhen Li ◽  
Lan Li Chen ◽  
Xiang Ju Han ◽  
Jing Xiao Lu

Amorphous silicon films prepared by PECVD on glass substrate has been crystallized by conventional furnace annealing (FA) at different temperatures. From the Raman spectra and scanning electronic microscope (SEM), it is found that the thin film grain size present quantum states with annealing temperature.


2011 ◽  
Vol 287-290 ◽  
pp. 1352-1355
Author(s):  
Qing Dong Chen ◽  
Jun Ping Wang ◽  
Yu Xiang Zhang

Porous silicon were prepared by electrochemical corrosion. Undoped and boron doped silicon films were deposited on quartz substrate、porous silicon and silicon substrate by PECVD,and were solid phase crystallized at different temperature and different hours. The microstructure of films before and after annealing were studied by Raman and XRD. The results show that:the crystallization of films deposited on porous silicon and monocrystalline silicon substrate are better than quartz substrate; The substrate which has silicon crystal lattice play an important role of seed crystal in the solid phase crystallization, the same grain orientation film can be grown on certain condition.


1996 ◽  
Vol 424 ◽  
Author(s):  
Reece Kingi ◽  
Yaozu Wang ◽  
Stephen Fonash ◽  
Osama Awadelkarim ◽  
Yuan-Mn Li

AbstractThree approaches to modifying the solid phase crystallization kinetics of amorphous silicon thin films are examined with the goal of reducing the thermal budget and improving the poly-Si quality for thin film transistor applications. The three approaches consist of (1) variations in the PECVD a-Si deposition parameters; (2) the application of pre-fumace-anneal surface treatments; and (3) using both rapid thermal annealing and furnace annealing at different temperatures. We also examine the synergism among these approaches.Results reveal that (1) film deposition dilution and dilution/temperature changes do not strongly affect crystallization time, but do affect grain size; (2) pre-anneal surface treatments can dramatically reduce the solid phase crystallization thermal budget for diluted films and act synergistically with deposition dilution or dilution/temperature effects; and (3) rapid thermal annealing leads to different crystallization kinetics from that seen for furnace annealing.


1982 ◽  
Vol 13 ◽  
Author(s):  
J. Narayan ◽  
O. W. Holland ◽  
G. L. Olson

ABSTRACTThe nature of residual damage in As+, Sb+, and In+ implanted silicon after CW laser and e− beam annealing has been studied using plan-view and cross-section electron microscopy. Lattice location of implanted atoms and their concentrations were determined by Rutherford backscattering and channeling techniques. Maximum substitutional concentrations achieved by furnace annealing in a temperature range of 500–600°C have been previously reported [1] and greatly exceeded the retrograde solubility limits for all dopants studied. Higher temperatures and SPE growth rates characteristic of electron or cw laser annealing did not lead to greater incorporation of dopant within the lattice and often resulted in dopant precipitation. Dopant segregation at the surface was sometimes observed at higher temperatures.


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