Ultra-Thin Zirconium Silicate Filmsc With Good Physical And Electrical Properties For Gate Dielectric Applications

2000 ◽  
Vol 648 ◽  
Author(s):  
Easwar Dharmarajan ◽  
Wen-Jie Qi ◽  
Renee Nieh ◽  
Laegu Kang ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Interface Quality ◽  
Good Thermal Stability ◽  
Cmos Scaling ◽  
Zirconium Silicate

AbstractThe need for alternative gate dielectrics to replace conventional SiO2 is increasing to facilitate further CMOS scaling. One of the most promising materials for use as an alternative gate dielectric is Zr silicate due to its thermodynamic stability on Si and its good interface quality with Si. In this study, ultra-thin Zr silicate films (45 – 60 Å thick) with different Zr compositions have been deposited on Si using magnetron reactive co-sputtering. The Zr composition was kept below the stoichiometric value of about 16% to prevent precipitation of ZrO2and to have Si rich films for better interface quality. Films were rapid thermal annealed in N2 ambient up to 9000C and Pt was used as the gate electrode. Electrical characterization of these films was done using HP 4156 and HP 4194 parameter analyzers. Based on these studies, we demonstrate Zr silicate films with equivalent oxide thickness (EOT) of less than 14 Å with gate leakage significantly lower thanSiO2 of similar thickness and hysteresis of < 20mV ( in a sweep from –3 to 3 V). The films exhibit good thermal stability on Si even after 900 0C annealing as shown by a minimal increase in EOT with annealing. TEM and XPS analyses show high quality Zr silicate films that remain stable and amorphous even at 900 0C.

Fabrication and Characterization of Directly-Assembled ZnO Nanowire Field Effect Transistors with Polymer Gate Dielectrics

2007 ◽  
Vol 7 (11) ◽  
pp. 4101-4105
Author(s):  
Ahnsook Yoon ◽  
Woong-Ki Hong ◽  
Takhee Lee
Keyword(s):  
Dielectric Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Electrical Characteristics ◽  
Zno Nanowire ◽  
Device Structure

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

2003 ◽  
Vol 765 ◽  
Author(s):  
Daewon Ha ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Leakage Current ◽  
Deposition Rate ◽  
Silicon Germanium ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Cmos Process ◽  
Gate Leakage ◽  
Process Technology ◽  
Cmos Scaling

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

Fabrication and Characterization of Directly-Assembled ZnO Nanowire Field Effect Transistors with Polymer Gate Dielectrics

2007 ◽  
Vol 7 (11) ◽  
pp. 4101-4105 ◽  
Author(s):  
Ahnsook Yoon ◽  
Woong-Ki Hong ◽  
Takhee Lee
Keyword(s):  
Dielectric Layer ◽  
Field Effect ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Electrical Characteristics ◽  
Zno Nanowire ◽  
Device Structure

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

Electrical Characterization of Oxynitrided Gate Dielectrics under Constant‐Current Fowler‐Nordheim Stress

1997 ◽  
Vol 144 (9) ◽  
pp. 3299-3304 ◽  
Author(s):  
T. K. Nguyen ◽  
L. M. Landsberger ◽  
S. Belkouch ◽  
C. Jean
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Constant Current

Process and Manufacturing Challenges for High-K Gate Stack Systems

1999 ◽  
Vol 567 ◽  
Author(s):  
M.C. Gilmer ◽  
T-Y Luo ◽  
H.R. Huff ◽  
M.D. Jackson ◽  
S. Kim ◽  
...  
Keyword(s):  
Silicon Surface ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Metal Electrode ◽  
Significant Variable ◽  
Tem Analysis ◽  
Physical Mechanisms ◽  
High K ◽  
Commercial Equipment

ABSTRACTA design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed in 100% or 10% O2 for different times and temperatures in conjunction with a previously prepared NH3 nitrided or 14N implanted silicon surface. Five metal electrode configurations—Ta, TaN, W, WN and TiN—were concurrently examined. Three additional silicon surface configurations were explored in conjunction with a more in-depth set of time and temperature anneals for Ta2O5. Electrical characterization of capacitors fabricated with the above high-K gate dielectrics, as well as SIMS and TEM analysis, indicate that the post high-K deposition annealing temperature was the most significant variable impacting the leakage current density, although there was minimal influence on the capacitance. Further studies are required, however, to clarify the physical mechanisms underlying the electrical data presented.

NANOSTRUCTURAL PROPERTIES OF La2O3/HfO2 GATE DIELECTRICS

2012 ◽  
Vol 26 (14) ◽  
pp. 1250080 ◽  
Author(s):  
A. BAHARI ◽  
A. RAMZANNEJAD
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Wide Band ◽  
Amorphous Structure ◽  
Boron Diffusion ◽  
Wide Band Gap ◽  
Good Thermal Stability ◽  
Force Microscopy ◽  
Alternative Material ◽  
High Dielectric

There are some issues such as tunneling, leakage currents and boron diffusion through the ultra thin SiO 2 which are threatening ultra thin SiO 2 dielectric as a good gate dielectric. A very obvious alternative material is HfO 2, due to its high dielectric constant, wide band gap and good thermal stability on silicon substrate. We have thus demonstrated a number of processes to synthesize La 2 O 3/ HfO 2 and studied its nano structural properties with using X-ray diffraction (XRD), Fourier transform infrared spectroscopy (FTIR), scanning electron microscopy (SEM) and atomic force microscopy (AFM) techniques. The obtained results show that La 2 O 3/ HfO 2 (at 500°C with amorphous structure) can be introduced as a good gate dielectric for the future of complementary metal insulator semiconductor (CMIS) device.

Current conduction of 0.72 nm equivalent-oxide-thickness LaO/HfO2 stacked gate dielectrics

2009 ◽  
Vol 95 (1) ◽  
pp. 012103 ◽  
Author(s):  
Chuan-Hsi Liu ◽  
Hung-Wen Chen ◽  
Shung-Yuan Chen ◽  
Heng-Sheng Huang ◽  
Li-Wei Cheng
Keyword(s):  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Current Conduction
Sign in / Sign up

Export Citation Format

Share Document