Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

2003 ◽  
Vol 765 ◽  
Author(s):  
Daewon Ha ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Leakage Current ◽  
Deposition Rate ◽  
Silicon Germanium ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Cmos Process ◽  
Gate Leakage ◽  
Process Technology ◽  
Cmos Scaling

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

2011 ◽  
Vol 88 (7) ◽  
pp. 1309-1311 ◽  
Author(s):  
C.H. Fu ◽  
K.S. Chang-Liao ◽  
Y.A. Chang ◽  
Y.Y. Hsu ◽  
T.H. Tzeng ◽  
...  
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Equivalent Oxide Thickness ◽  
Gate Leakage ◽  
High K ◽  
High K Gate Dielectric

Ultra-Thin Zirconium Silicate Filmsc With Good Physical And Electrical Properties For Gate Dielectric Applications

2000 ◽  
Vol 648 ◽  
Author(s):  
Easwar Dharmarajan ◽  
Wen-Jie Qi ◽  
Renee Nieh ◽  
Laegu Kang ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Interface Quality ◽  
Good Thermal Stability ◽  
Cmos Scaling ◽  
Zirconium Silicate

AbstractThe need for alternative gate dielectrics to replace conventional SiO2 is increasing to facilitate further CMOS scaling. One of the most promising materials for use as an alternative gate dielectric is Zr silicate due to its thermodynamic stability on Si and its good interface quality with Si. In this study, ultra-thin Zr silicate films (45 – 60 Å thick) with different Zr compositions have been deposited on Si using magnetron reactive co-sputtering. The Zr composition was kept below the stoichiometric value of about 16% to prevent precipitation of ZrO2and to have Si rich films for better interface quality. Films were rapid thermal annealed in N2 ambient up to 9000C and Pt was used as the gate electrode. Electrical characterization of these films was done using HP 4156 and HP 4194 parameter analyzers. Based on these studies, we demonstrate Zr silicate films with equivalent oxide thickness (EOT) of less than 14 Å with gate leakage significantly lower thanSiO2 of similar thickness and hysteresis of < 20mV ( in a sweep from –3 to 3 V). The films exhibit good thermal stability on Si even after 900 0C annealing as shown by a minimal increase in EOT with annealing. TEM and XPS analyses show high quality Zr silicate films that remain stable and amorphous even at 900 0C.

Zr Oxide Based Gate Dielectrics with Equivalent SiO2 Thickness of Less than 1.0 nm and Device Integration with Pt Gate Electrode

2000 ◽  
Vol 611 ◽  
Author(s):  
Yanjun Ma ◽  
Yoshi Ono
Keyword(s):  
Gate Dielectric ◽  
Process Integration ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Cmos Process ◽  
Metal Gate ◽  
Leakage Currents ◽  
Gate Electrodes ◽  
Device Integration ◽  
Dual Metal

ABSTRACTZrO2 films are investigated as an alternative to SiO2 gate dielectric below 1.5nm. A maximum accumulation capacitance ∼35 fF/μm2 with a leakage current of less than 0.1 A/cm2 has been achieved for a 3 nm Zr-O film, suggesting that ZrO2 can be scaled to below an equivalent oxide thickness of 0.5 nm. Al and Si doping is also investigated to reduce leakage currents and to increase the crystallization temperature of the film. Submicron MOSFETs with TiN or Pt gate electrodes have been fabricated with these gate dielectrics with excellent characteristics, demonstrating the feasibility of CMOS process integration. In particular, Pt damascene gate PMOS is shown to have the proper threshold voltage for dual metal gate CMOS application.

scholarly journals Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet
Keyword(s):  
Dielectric Constant ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage ◽  
Mos Devices ◽  
High K ◽  
Carrier Trap ◽  
High Dielectric ◽  
Very High ◽  
Tunnelling Current

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

The Effect of Ternary Material (Zr, Y, and O) High-k Gate Dielectrics

2013 ◽  
Vol 699 ◽  
pp. 422-425 ◽  
Author(s):  
K.C. Lin ◽  
C.H. Chou ◽  
J.Y. Chen ◽  
C.J. Li ◽  
J.Y. Huang ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Electrical Property ◽  
Leakage Current ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Gate Dielectrics ◽  
Bottom Layer ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
High K

In this research, the Y2O3 layer is doped with the zirconium through co-sputtering and rapid thermal annealing (RTA) at 550°C, 700°C, and 850°C. Then the Al electrode is deposited to generate two kinds of structures, Al/ZrN/ Y2O3/ Y2O3+Zr/p-Si and Al/ZrN/ Y2O3+Zr/ Y2O3/p-Si. According to the XRD results, when Zr was doped on the upper layer, the crystallization phenomenon was more significant than Zr was at the bottom layer, meaning that Zr may influence the diffusion of the oxygen. The AFM also shows that the surface roughness of Zr has worse performance. For the electrical property, the influence to overall leakage current is increased because the equivalent oxide thickness (EOT) is thinner.

scholarly journals AlGaN/GaN MIS-HEMT with PECVD SiNx, SiON, SiO2 as Gate Dielectric and Passivation Layer

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 416 ◽  
Author(s):  
Kuiwei Geng ◽  
Ditao Chen ◽  
Quanbin Zhou ◽  
Hong Wang
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
Deep Trap ◽  
Trap Density ◽  
Interface Traps ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Metal Insulator ◽  
Current Collapse ◽  
Gate Leakage Current Density

Three different insulator layers SiNx, SiON, and SiO2 were used as a gate dielectric and passivation layer in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMT). The SiNx, SiON, and SiO2 were deposited by a plasma-enhanced chemical vapor deposition (PECVD) system. Great differences in the gate leakage current, breakdown voltage, interface traps, and current collapse were observed. The SiON MIS-HEMT exhibited the highest breakdown voltage and Ion/Ioff ratio. The SiNx MIS-HEMT performed well in current collapse but exhibited the highest gate leakage current density. The SiO2 MIS-HEMT possessed the lowest gate leakage current density but suffered from the early breakdown of the metal–insulator–semiconductor (MIS) diode. As for interface traps, the SiNx MIS-HEMT has the largest shallow trap density and the lowest deep trap density. The SiO2 MIS-HEMT has the largest deep trap density. The factors causing current collapse were confirmed by Photoluminescence (PL) spectra. Based on the direct current (DC) characteristics, SiNx and SiON both have advantages and disadvantages.

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