Shallow Junctions for Sub-100 Nm Cmos Technology

2001 ◽  
Vol 669 ◽  
Author(s):  
Veerle Meyssen ◽  
Peter Stolk ◽  
Jeroen van Zijl ◽  
Jurgen van Berkum ◽  
Willem van de Wijgert ◽  
...  

ABSTRACTThis paper studies the use of ion implantation and rapid thermal annealing for the fabrication of shallow junctions in sub-100 nm CMOS technology. Spike annealing recipes were optimized on the basis of delta-doping diffusion experiments and shallow junction characteristics. In addition, using GeF2 pre-amorphization implants in combination with low-energy BF2 and spike annealing, p-type junctions depths of 30 nm were obtained with sheet resistances as low as 390 Ω/sq. The combined finetuning of implantation and annealing conditions is expected to enable junction scaling into the 70-nm CMOS technology node.

1989 ◽  
Vol 147 ◽  
Author(s):  
Samuel Chen ◽  
S.-Tong Lee ◽  
G. Braunstein ◽  
G. Rajeswaran ◽  
P. Fellinger

AbstractDefects induced by ion implantation and subsequent annealing are found to either promote or suppress layer intermixing in Ill-V compound semiconductor superlattices (SLs). We have studied this intriguing relationship by examining how implantation and annealing conditions affect defect creation and their relevance to intermixing. Layer intermixing has been induced in SLs implanted with 220 keV Si+ at doses < 1 × 1014 ions/cm2 and annealed at 850°C for 3 hrs or 1050°C for 10 s. Upon furnace annealing, significant Si in-diffusion is observed over the entire intermixed region, but with rapid thermal annealing layer intermixing is accompanied by negligible Si movement. TEM showed that the totally intermixed layers are centered around a buried band of secondary defects and below the Si peak position. In the nearsurface region layer intermixing is suppressed and is only partially completed at ≤1 × 1015 Si/cm2. This inhibition is correlated to a loss of the mobile implantation-induced defects, which are responsible for intermixing.


1985 ◽  
Vol 52 ◽  
Author(s):  
D. L. Kwong ◽  
N. S. Alvi ◽  
Y. H. Ku ◽  
A. W. Cheung

ABSTRACTDouble-diffused shallow junctions have been formed by ion implantation of both phosphorus and arsenic ions into silicon substrates and rapid thermal annealing. Experimental results on defect removal, impurity activation and redistribution, effects of Si preamorphization, and electrical characteristics of Ti-silicided junctions are presented.


2004 ◽  
Vol 03 (04n05) ◽  
pp. 425-430 ◽  
Author(s):  
A. MARKWITZ ◽  
S. JOHNSON ◽  
M. RUDOLPHI ◽  
H. BAUMANN

A combination of 10 keV 13 C low energy ion implantation and electron beam rapid thermal annealing (EB-RTA) is used to fabricate silicon carbide nanostructures on (100) silicon surfaces. These large ellipsoidal features appear after EB-RTA at 1000°C for 15 s. Prior to annealing, the silicon surfaces are virgin-like flat. Atomic force microscopy was used to study the morphology of these structures and it was found that the diameter and number of nanoboulders are linearly dependent on the implantation fluence. Further, a linear relationship between nanoboulder diameter and spacing suggests crystal coarsening is a fundamental element in the growth mechanism.


1990 ◽  
Vol 182 ◽  
Author(s):  
B. Raicu ◽  
M.I. Current ◽  
W.A. Keenan ◽  
D. Mordo ◽  
R. Brennan ◽  
...  

AbstractHighly conductive p+-polysilicon films were fabricated over Si(100) and SiO2 surfaces using high-dose ion implantation and rapid thermal annealing. Resistivities close to that of single crystal silicon were achieved. These films were characterized by a variety of electrical and optical techniques as well as SIMS and cross-section TEM.


1990 ◽  
Vol 181 ◽  
Author(s):  
L. Niewöhner ◽  
D. Depta

ABSTRACTFormation of CoSi2 using the technique of ion implantation through metal (ITM) and subsequent appropriate rapid thermal annealing is described. Silicide morphology is investigated by SEM and TEM. SIMS and RBS are used to determine dopant distribution and junction depth. Self-aligned CoSi2/n+p diodes produced in this technique are presented.


2012 ◽  
Vol 195 ◽  
pp. 274-276 ◽  
Author(s):  
Philipp Hönicke ◽  
Matthias Müller ◽  
Burkhard Beckhoff

The continuing shrinking of the component dimensions in ULSI technology requires junction depths in the 20-nm regime and below to avoid leakage currents. These ultra shallow dopant distributions can be formed by ultra-low energy (ULE) ion implantation. However, accurate measurement techniques for ultra-shallow dopant profiles are required in order to characterize ULE implantation and the necessary rapid thermal annealing (RTA) processes.


Sign in / Sign up

Export Citation Format

Share Document