Vibrating RF MEMS for Low Power Communications

2002 ◽  
Vol 741 ◽  
Author(s):  
Clark T.-C. Nguyen
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Rf Mems ◽  
Single Chip ◽  
Low Loss ◽  
Wireless Transceivers ◽  
Reduce Power Consumption ◽  
Front End ◽  
Communication Circuits ◽  
Transistor Circuits

ABSTRACTMicromechanical communication circuits fabricated via IC-compatible MEMS technologies and capable of low-loss filtering, mixing, switching, and frequency generation, are described with the intent to miniaturize wireless transceivers. Possible transceiver front-end architectures are then presented that use these micromechanical circuits in large quantities to substantially reduce power consumption. Technologies that integrate MEMS and transistor circuits into single-chip systems are then reviewed with an eye towards the possibility of single-chip communication transceivers.

IMPROVED ALGORITHMS FOR LOW POWER MULTIPLEXOR DECOMPOSITION

2005 ◽  
Vol 14 (06) ◽  
pp. 1085-1099
Author(s):  
SHAOFA YANG ◽  
HON WAI LEONG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Optimization Procedure ◽  
Decomposition Algorithm ◽  
Major Portion ◽  
Decomposition Problem ◽  
Reduce Power Consumption ◽  
Speed Up

It has been estimated that multiplexors (MUXes) make up a major portion of the circuitry in a typical chip. Therefore, to reduce power consumption of a chip, it is important to consider the design of MUXes that consumes less power. This is called the low power MUX decomposition problem and has been studied in Ref. 1. This paper improves on the results of Ref. 1 in two ways: (a) we propose a method to speed up the algorithms in Ref. 1, and (b) we propose a post-optimization procedure to further reduce the overall power dissipation of decompositions obtained by any MUX decomposition algorithm. Using this post-optimization procedure, we have been able to further reduce the power dissipation results of Ref. 1.

scholarly journals Silicon nanomembrane phototransistor flipped with multifunctional sensors toward smart digital dust

2020 ◽  
Vol 6 (18) ◽  
pp. eaaz6511 ◽  
Author(s):  
Gongjin Li ◽  
Zhe Ma ◽  
Chunyu You ◽  
Gaoshan Huang ◽  
Enming Song ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Flexible Electronics ◽  
Large Scale ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Stimuli Responsive ◽  
Single Chip ◽  
Detection Mechanism ◽  
Silicon Nanomembrane

The sensing module that converts physical or chemical stimuli into electrical signals is the core of future smart electronics in the post-Moore era. Challenges lie in the realization and integration of different detecting functions on a single chip. We propose a new design of on-chip construction for low-power consumption sensor, which is based on the optoelectronic detection mechanism with external stimuli and compatible with CMOS technology. A combination of flipped silicon nanomembrane phototransistors and stimuli-responsive materials presents low-power consumption (CMOS level) and demonstrates great functional expansibility of sensing targets, e.g., hydrogen concentration and relative humidity. With a device-first, wafer-compatible process introduced for large-scale silicon flexible electronics, our work shows great potential in the development of flexible and integrated smart sensing systems for the realization of Internet of Things applications.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

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