Monolithically Integrated p- & n- Channel Thin Film Transistors of Nanocrystalline Silicon on Plastic Substrates

2004 ◽  
Vol 808 ◽  
Author(s):  
I-Chun Cheng ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Structural Evolution ◽  
Nanocrystalline Silicon ◽  
Leakage Currents ◽  
Plastic Substrates ◽  
Monolithically Integrated ◽  
Glass Substrates ◽  
Electron Field

ABSTRACTInverters made of monolithically integrated p- and n-channel thin film transistors of nanocrystalline silicon were demonstrated on both Corning 1737 glass and Kapton E polyimide substrates. The TFT's geometry is staggered top-gate, bottom-source/rain. A nc-Si:H seed layer promotes the structural evolution of the nc-Si:H channel. Electron field-effect mobilities of 15 - 30 cm2V−1s-1 and hole mobilities of 0.15 - 0.35 cm2V−1s−1 were obtained. Slightly lower carrier mobilities were observed in the TFTs made on polyimide than on glass substrates. High gate leakage currents and offsets between the supply HIGH voltages and the output voltages in the inverters indicate that the low-temperature gate dielectric needs improvement.

Evolution of Nanocrystalline Silicon Layers Deposited at 150°C for Thin Film Transistor Channels

2003 ◽  
Vol 769 ◽  
Author(s):  
I-Chun Cheng ◽  
Steven Allen ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Carrier Mobility ◽  
Thin Film Transistor ◽  
Structural Evolution ◽  
Nanocrystalline Silicon ◽  
Crystalline Layer ◽  
Electron Field ◽  
High Carrier Mobility ◽  
High Carrier ◽  
Made In

AbstractThin film transistors of nanocrystalline silicon (nc-Si:H) are made in the staggered topgate, bottom-source/drain geometry. To achieve both high carrier mobility and low off current, the nc-Si:H channel material must be kept thin but comprise a contiguous 10-nm thick crystalline layer at its top. We study this electrically most interesting top layer of the nc-Si:H channel film by AFM and SEM. Introducing an nc-Si:H seed layer underneath the TFT promotes the structural evolution of the nc-Si:H channel layer and raises the electron field effect mobility up to 40 cm2V-1s-1.

Thin-Film Transistors on PET at 100°C

2002 ◽  
Vol 715 ◽  
Author(s):  
J.P. Conde ◽  
P. Alpuim ◽  
V. Chu
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Contact Layer ◽  
Processing Temperature ◽  
Silicon Thin Film ◽  
Glass Substrates ◽  
Hydrogen Dilution ◽  
Polyethylene Terephthalate Substrate

AbstractBottom-gate amorphous silicon thin-film transistors were fabricated on a polyethylene terephthalate substrate. The maximum processing temperature was 100°C. The transistor characteristics are comparable, although still inferior, to those of standard amorphous silicon transistors fabricated on glass substrates. To obtain these characteristics, an extended anneal the processing temperature was required. The devices were fabricated using separately optimized low-temperature active layer, contact layer and gate dielectric layer. To achieve good electronic properties for these layers, hydrogen dilution was required.

Impact of Silicon Nitride Gate Dielectric Composition on the Stability of Low Temperature Nanocrystalline Silicon Thin Film Transistors

2019 ◽  
Vol 35 (4) ◽  
pp. 73-79
Author(s):  
Mohammad Esmaeili-Rad ◽  
Gholamreza Chaji ◽  
Flora Li ◽  
Maryam Moradi ◽  
Andrei Sazonov ◽  
...  
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Nanocrystalline Silicon ◽  
Silicon Thin Film ◽  
The Stability

Stability of nanocrystalline silicon bottom-gate thin film transistors with silicon nitride gate dielectric

2007 ◽  
Vol 102 (6) ◽  
pp. 064512 ◽  
Author(s):  
Mohammad R. Esmaeili-Rad ◽  
Flora Li ◽  
Andrei Sazonov ◽  
Arokia Nathan
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Nanocrystalline Silicon ◽  
Bottom Gate

Fabrication of a-Si:H Tfts at 120°C on Flexible Polyimide Substrates

1999 ◽  
Vol 558 ◽  
Author(s):  
Andrei Sazonov ◽  
Arokia Nathan ◽  
R.V.R. Murthy ◽  
S.G. Chamberlain
Keyword(s):  
Thin Film ◽  
Gate Dielectric ◽  
Low Cost ◽  
Thin Film Transistor ◽  
Performance Comparison ◽  
Hydrogen Gas ◽  
Large Area ◽  
Plastic Substrates ◽  
Glass Substrates ◽  
Contact Metallization

ABSTRACTThe fabrication of large-area thin-film transistor (TFT) arrays on thin flexible plastic substrates requires deposition of thin film layers at relatively low temperatures since the upper working temperature of low-cost plastic films should not exceed ∼200°C. In this paper, we report a fabrication process of a-Si:H TFTs at 120°C on flexible polyimide substrates for large-area imaging applications.Kapton HN (DuPont) films 50 and 125 μm thick and 3 inches in diameter, were used as substrates. Both sides of the polyimide substrate were first covered with 0.5 μm thick a-SiNx. The TFT structure includes: 120 nm thick room-temperature sputtered Al gate, 250 nm thick PECVD deposited a-SiNx for the gate dielectric, 50 nm thick a-Si:H deposited by PECVD from silane-hydrogen gas mixture, 50 nm thick n+ a-Si:H source- and drain contacts, and roomtemperature sputtered Al top contact metallization. We used dry etching for all layers except for the gate and top metal, which were patterned using wet etchants. For purpose of TFT performance comparison, Coming 7059 glass substrates were used.The performance of the fabricated TFT and its improvement with use of optimized a-Si:H and a-SiNx quality will be presented along with a discussion of the intrinsic mechanical stress in the thin film layers will also be discussed.

Low-temperature processable inherently photosensitive polyimide gate dielectric for organic thin-film transistors: Synthesis, characterization, and application to transistors

2005 ◽  
Vol 20 (4) ◽  
pp. 931-939 ◽  
Author(s):  
Seungmoon Pyo ◽  
Hyunsam Son ◽  
Mi Hye Yi
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Low Cost ◽  
Polyimide Film ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Aromatic Diamines ◽  
Plastic Substrates

Low-temperature processable inherently photosensitive polyimide was prepared from a dianhydride, 3,3′,4,4′-benzophenone tetracarboxylic dianhydride, and aromatic diamines, 4,4′-diamino-3,3′dimethyl-diphenylmethane, through a polycondensation reaction, followed by a chemical imidization method. The photosensitive polyimide cured at 180 °C is used as a gate dielectric to fabricate flexible organic thin-film transistors with pentacene as an active semiconductor on polyethersulfone substrate. With the inherently photosensitive polyimide, the access to the gate electrode could be created easily without complicated and expensive lithographic techniques. A field effect carrier mobility of 0.007 cm2/V s was obtained for the pentacene organic thin-film transistors (OTFTs) with the photo-patterned polyimide as a gate dielectric. More detailed analysis for the pentacene OTFTs will be given with electrical properties of the thin polyimide film. Low-temperature processability and patternability of the polyimide give us more freedom to choose plastic substrates in OTFTs and facilitate the realization of low-cost organic electronics.

Hot-Wire Deposited Nanocrystalline Silicon TFTs on Plastic Substrates

2007 ◽  
Vol 989 ◽  
Author(s):  
Farhad Taghibakhsh ◽  
Michael M. Adachi ◽  
Karim S. Karim
Keyword(s):  
Vapor Deposition ◽  
Thermal Damage ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Nanocrystalline Silicon ◽  
Field Effect Mobility ◽  
Hot Wire ◽  
Current Ratio ◽  
Plastic Substrates ◽  
Electron Field

AbstractHot-wire chemical vapor deposition (HWCVD) technique was used to deposit nanocrystalline silicon (nc-Si) thin film transistors (TFT) on thin polyimide sheets. Two straight tantalum filaments at 1850°C with a substrate to filament distance of 4 cm was used to deposit HWCVD nc-Si with no thermal damage to plastic sheet. Top-gate staggered TFTs were fabricated at 150°C and 250°C using a HWCVD nc-Si channel, PECVD silicon nitride gate dielectric, and microcrystalline n+ drain/source contacts. Leakage current of 3.3×10-12 A, switching current ratio of 3×106, and sub threshold swing of 0.51 V/decade were obtained for TFTs with aspect ratio of 1400 µm / 100 µm fabricated at 150°C. The highest electron field effect mobility was found to be 0.3 cm2/V.s observed for TFTs deposited at lower substrate temperature. Measurements showed superior threshold voltage stability of HW nc-Si TFTs over their amorphous silicon (a-Si) counterparts.

Sign in / Sign up

Export Citation Format

Share Document