An Advanced High-k Transistor Utilizing Metal-Organic Precursors in an ALD Deposition of Hafnium Oxide and Hafnium Silicate with Ozone as Oxidizer

2004 ◽  
Vol 811 ◽  
Author(s):  
J. Gutt ◽  
G.A. Brown ◽  
Yoshi Senzaki ◽  
Seung Park
Keyword(s):  
Hafnium Oxide ◽  
High Performance ◽  
Gate Dielectric ◽  
Electrical Characterization ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Hafnium Silicate ◽  
High K ◽  
Metal Organic

AbstractThe International Technology Roadmap for Semiconductors (ITRS) has projected that continued scaling of planar CMOS technology to the 65nm node and beyond will require development of high-k films for transistor gate dielectric applications to allow further scaling of overall device sizes according to Moore's Law [1]. Researchers have recently been studying hafnium-based high-k dielectrics as an alternative to SiO2 [2]. The method of deposition of these films has been found to impact the applicability of the films for both low standby power and high performance applications [3]. Atomic Layer Deposition (ALD) has been among the more widely studied deposition techniques for these films, but previous work has emphasized ALD utilizing inorganic precursors [4]. In this paper, we shall describe a process in which hafnium oxide and hafnium silicate films were deposited from alternating pulses of volatile metal-organic Hf/Si liquid precursors and ozone on 200mm diameter Si substrates using a single wafer ALD system. Electrical characterization of the films is presented, including equivalent oxide thickness (EOT), gate leakage, and electron mobility data, showing an achievement of EOT's ranging from 1.19 to 1.69 nm with high field mobilities from 74% to more than 90% of that of SiO2 (2.1 nm film), and Jg in the range of 80mA to 3 A/cm2.

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

Electrical Characterization of Epitaxial Graphene Field-Effect Transistors with High-k Al2O3 Gate Dielectric Fabricated on SiC Substrates

2015 ◽  
Vol 821-823 ◽  
pp. 937-940 ◽  
Author(s):  
Toby Hopf ◽  
Konstantin Vassilevski ◽  
Enrique Escobedo-Cousin ◽  
Peter King ◽  
Nicholas G. Wright ◽  
...  
Keyword(s):  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Atomic Layer ◽  
Epitaxial Graphene ◽  
Vacuum Sublimation ◽  
Layer Deposition ◽  
High K

Top-gated field-effect transistors have been created from bilayer epitaxial graphene samples that were grown on SiC substrates by a vacuum sublimation approach. A high-quality dielectric layer of Al2O3was grown by atomic layer deposition to function as the gate oxide, with an e-beam evaporated seed layer utilized to promote uniform growth of Al2O3over the graphene. Electrical characterization has been performed on these devices, and temperature-dependent measurements yielded a rise in the maximum transconductance and a significant shifting of the Dirac point as the operating temperature of the transistors was increased.

scholarly journals Comparative Study ofSiO2,Al2O3, and BeO Ultrathin Interfacial Barrier Layers in Si Metal-Oxide-Semiconductor Devices

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
J. H. Yum ◽  
J. Oh ◽  
Todd. W. Hudnall ◽  
C. W. Bielawski ◽  
G. Bersuker ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Performance ◽  
Field Effect Transistors ◽  
Beryllium Oxide ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Effective Electron

In a previous study, we have demonstrated that beryllium oxide (BeO) film grown by atomic layer deposition (ALD) on Si and III-V MOS devices has excellent electrical and physical characteristics. In this paper, we compare the electrical characteristics of inserting an ultrathin interfacial barrier layer such as SiO2, Al2O3, or BeO between the HfO2gate dielectric and Si substrate in metal oxide semiconductor capacitors (MOSCAPs) and n-channel inversion type metal oxide semiconductor field effect transistors (MOSFETs). Si MOSCAPs and MOSFETs with a BeO/HfO2gate stack exhibited high performance and reliability characteristics, including a 34% improvement in drive current, slightly better reduction in subthreshold swing, 42% increase in effective electron mobility at an electric field of 1 MV/cm, slightly low equivalent oxide thickness, less stress-induced flat-band voltage shift, less stress induced leakage current, and less interface charge.

scholarly journals High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

2012 ◽  
Vol 7 (1) ◽  
pp. 431 ◽  
Author(s):  
Szu-Hung Chen ◽  
Wen-Shiang Liao ◽  
Hsin-Chia Yang ◽  
Shea-Jue Wang ◽  
Yue-Gie Liaw ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
High K ◽  
High K Gate Dielectric

scholarly journals Electrical Characterization of Postmetal Annealed Ultrathin TiN Gate Electrodes in Si MOS Capacitors

2016 ◽  
Vol 2016 ◽  
pp. 1-4 ◽  
Author(s):  
Z. N. Khan ◽  
S. Ahmed ◽  
M. Ali
Keyword(s):  
Electrical Characterization ◽  
Atomic Layer ◽  
Device Fabrication ◽  
Process Window ◽  
Gate Stacks ◽  
Mos Capacitors ◽  
Hafnium Silicate ◽  
Gate Electrodes ◽  
Layer Deposition ◽  
Tin Metal

Focusing on sub-10 nm Silicon CMOS device fabrication technology, we have incorporated ultrathin TiN metal gate electrode in Hafnium Silicate (HfSiO) based metal-oxide capacitors (MOSCAP) with carefully chosen Atomic Layer Deposition (ALD) process parameters. Gate element of the device has undergone a detailed postmetal annealed sequence ranging from 100°C to 1000°C. The applicability of ultrathin TiN on gate electrodes is established through current density versus voltage (J-V), resistance versus temperature (R-T), and permittivity versus temperature analysis. A higher process window starting from 600°C was intentionally chosen to understand the energy efficient behavior expected from ultrathin gate metallization and its unique physical state with shrinking thickness. The device characteristics in form of effective electronic mobility as a function of inverse charge density were also found better than those conventional gate stacks used for EOT scaling.

Design, Simulation and Testing of High Density, High Current Micro-machined Embedded Capacitors

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000515-000534
Author(s):  
Aubrey Beal ◽  
C. Stevens ◽  
T. Baginski ◽  
M. Hamilton ◽  
R. Dean
Keyword(s):  
Integrated Circuits ◽  
Hafnium Oxide ◽  
Implementation Strategies ◽  
Atomic Layer ◽  
High Density ◽  
Embedded Capacitors ◽  
Passive Devices ◽  
Layer Deposition ◽  
High K ◽  
High K Materials

Due to increasing speed, density and number of signal paths in integrated circuits, motivations for high density capacitors capable of quickly sourcing large amounts of current have led to many design and fabrication investigations. This work outlines continued efforts to achieve devices which meet these stringent requirements and are compatible with standard silicon fabrication processes as well as silicon interposer technologies. Previous work has been further developed resulting in devices exhibiting greater capacitance values by employing geometries which maximize surface area. The Atomic Layer Deposition (ALD) of thin layered high K materials, such as Hafnium Oxide, as opposed to previous silicon-dioxide based devices effectively increased the capacitance per unit area of the structures. This paper outlines the design, fabrication, and testing of high density micro-machined embedded capacitors capable of quickly sourcing (i.e. risetimes greater than 100A/nsec) high currents (i.e. greater than 100A). These devices were successfully simulated then tested using a standard ringdown procedure. Generally, the resulting device characterization found during testing stages strongly correlates to the expected simulated device behavior. Subsequent descriptions and design challenges encountered during fabrication, testing and integration of these passive devices are outlined, as well as potential device integration and implementation strategies for use in silicon interposers. The modification and revision of several device generations is documented and presented. Increased device capacitive density, maximized current capabilities and minimized effects of series inductance and resistance are presented. These resulting thin, capacitive structures exhibit compatibility with Si interposer technology.

scholarly journals Conformal High-K Dielectric Coating of Suspended Single-Walled Carbon Nanotubes by Atomic Layer Deposition

Nanomaterials ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 1085 ◽  
Author(s):  
Kemelbay ◽  
Tikhonov ◽  
Aloni ◽  
Kuykendall
Keyword(s):  
Carbon Nanotubes ◽  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Ambient Conditions ◽  
Nucleation Layer ◽  
Layer Deposition ◽  
High K ◽  
High K Dielectric

As one of the highest mobility semiconductor materials, carbon nanotubes (CNTs) have been extensively studied for use in field effect transistors (FETs). To fabricate surround-gate FETs— which offer the best switching performance—deposition of conformal, weakly-interacting dielectric layers is necessary. This is challenging due to the chemically inert surface of CNTs and a lack of nucleation sites—especially for defect-free CNTs. As a result, a technique that enables integration of uniform high-k dielectrics, while preserving the CNT’s exceptional properties is required. In this work, we show a method that enables conformal atomic layer deposition (ALD) of high-k dielectrics on defect-free CNTs. By depositing a thin Ti metal film, followed by oxidation to TiO2 under ambient conditions, a nucleation layer is formed for subsequent ALD deposition of Al2O3. The technique is easy to implement and is VLSI-compatible. We show that the ALD coatings are uniform, continuous and conformal, and Raman spectroscopy reveals that the technique does not induce defects in the CNT. The resulting bilayer TiO2/Al2O3 thin-film shows an improved dielectric constant of 21.7 and an equivalent oxide thickness of 2.7 nm. The electrical properties of back-gated and top-gated devices fabricated using this method are presented.

Sign in / Sign up

Export Citation Format

Share Document