Implementation of a Decoupled Digital Feedback Control Architecture on an Arduino - Free RTOS Real-Time Embedded System for Input Delay Robotic Servomechanisms

2021 ◽  
Vol 14 (4) ◽  
pp. 201
Author(s):  
Jeanne Loga Nga Fouda ◽  
Charles Hubert Kom ◽  
Bertrand Moffo Lonla ◽  
Jean Mbihi
1995 ◽  
Vol 34 (05) ◽  
pp. 475-488
Author(s):  
B. Seroussi ◽  
J. F. Boisvieux ◽  
V. Morice

Abstract:The monitoring and treatment of patients in a care unit is a complex task in which even the most experienced clinicians can make errors. A hemato-oncology department in which patients undergo chemotherapy asked for a computerized system able to provide intelligent and continuous support in this task. One issue in building such a system is the definition of a control architecture able to manage, in real time, a treatment plan containing prescriptions and protocols in which temporal constraints are expressed in various ways, that is, which supervises the treatment, including controlling the timely execution of prescriptions and suggesting modifications to the plan according to the patient’s evolving condition. The system to solve these issues, called SEPIA, has to manage the dynamic, processes involved in patient care. Its role is to generate, in real time, commands for the patient’s care (execution of tests, administration of drugs) from a plan, and to monitor the patient’s state so that it may propose actions updating the plan. The necessity of an explicit time representation is shown. We propose using a linear time structure towards the past, with precise and absolute dates, open towards the future, and with imprecise and relative dates. Temporal relative scales are introduced to facilitate knowledge representation and access.


1999 ◽  
Vol 7 (4) ◽  
pp. 391-404 ◽  
Author(s):  
TONG FANG ◽  
MOHSEN A. JAFARI ◽  
AHMAD SAFARI ◽  
STEPHEN C. DANFORTH

2020 ◽  
Vol 5 (6) ◽  
pp. 1156-1162
Author(s):  
Anirudh Gautam ◽  
Jason A. Brant ◽  
Michael J. Ruckenstein ◽  
Steven J. Eliades

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 13
Author(s):  
Balaji M ◽  
Chandrasekaran M ◽  
Vaithiyanathan Dhandapani

A Novel Rail-Network Hardware with simulation facilities is presented in this paper. The hardware is designed to facilitate the learning of application-oriented, logical, real-time programming in an embedded system environment. The platform enables the creation of multiple unique programming scenarios with variability in complexity without any hardware changes. Prior experimental hardware comes with static programming facilities that focus the students’ learning on hardware features and programming basics, leaving them ill-equipped to take up practical applications with more real-time constraints. This hardware complements and completes their learning to help them program real-world embedded systems. The hardware uses LEDs to simulate the movement of trains in a network. The network has train stations, intersections and parking slots where the train movements can be controlled by using a 16-bit Renesas RL78/G13 microcontroller. Additionally, simulating facilities are provided to enable the students to navigate the trains by manual controls using switches and indicators. This helps them get an easy understanding of train navigation functions before taking up programming. The students start with simple tasks and gradually progress to more complicated ones with real-time constraints, on their own. During training, students’ learning outcomes are evaluated by obtaining their feedback and conducting a test at the end to measure their knowledge acquisition during the training. Students’ Knowledge Enhancement Index is originated to measure the knowledge acquired by the students. It is observed that 87% of students have successfully enhanced their knowledge undergoing training with this rail-network simulator.


2021 ◽  
Vol 11 (11) ◽  
pp. 4940
Author(s):  
Jinsoo Kim ◽  
Jeongho Cho

The field of research related to video data has difficulty in extracting not only spatial but also temporal features and human action recognition (HAR) is a representative field of research that applies convolutional neural network (CNN) to video data. The performance for action recognition has improved, but owing to the complexity of the model, some still limitations to operation in real-time persist. Therefore, a lightweight CNN-based single-stream HAR model that can operate in real-time is proposed. The proposed model extracts spatial feature maps by applying CNN to the images that develop the video and uses the frame change rate of sequential images as time information. Spatial feature maps are weighted-averaged by frame change, transformed into spatiotemporal features, and input into multilayer perceptrons, which have a relatively lower complexity than other HAR models; thus, our method has high utility in a single embedded system connected to CCTV. The results of evaluating action recognition accuracy and data processing speed through challenging action recognition benchmark UCF-101 showed higher action recognition accuracy than the HAR model using long short-term memory with a small amount of video frames and confirmed the real-time operational possibility through fast data processing speed. In addition, the performance of the proposed weighted mean-based HAR model was verified by testing it in Jetson NANO to confirm the possibility of using it in low-cost GPU-based embedded systems.


Sensors ◽  
2021 ◽  
Vol 21 (12) ◽  
pp. 3955
Author(s):  
Jung-Cheng Yang ◽  
Chun-Jung Lin ◽  
Bing-Yuan You ◽  
Yin-Long Yan ◽  
Teng-Hu Cheng

Most UAVs rely on GPS for localization in an outdoor environment. However, in GPS-denied environment, other sources of localization are required for UAVs to conduct feedback control and navigation. LiDAR has been used for indoor localization, but the sampling rate is usually too low for feedback control of UAVs. To compensate this drawback, IMU sensors are usually fused to generate high-frequency odometry, with only few extra computation resources. To achieve this goal, a real-time LiDAR inertial odometer system (RTLIO) is developed in this work to generate high-precision and high-frequency odometry for the feedback control of UAVs in an indoor environment, and this is achieved by solving cost functions that consist of the LiDAR and IMU residuals. Compared to the traditional LIO approach, the initialization process of the developed RTLIO can be achieved, even when the device is stationary. To further reduce the accumulated pose errors, loop closure and pose-graph optimization are also developed in RTLIO. To demonstrate the efficacy of the developed RTLIO, experiments with long-range trajectory are conducted, and the results indicate that the RTLIO can outperform LIO with a smaller drift. Experiments with odometry benchmark dataset (i.e., KITTI) are also conducted to compare the performance with other methods, and the results show that the RTLIO can outperform ALOAM and LOAM in terms of exhibiting a smaller time delay and greater position accuracy.


2021 ◽  
Vol 165 ◽  
pp. 112218
Author(s):  
Rohit Kumar ◽  
Pramila Gautam ◽  
Shivam Gupta ◽  
R.L. Tanna ◽  
Praveenlal Edappala ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 469
Author(s):  
Hyun Woo Oh ◽  
Ji Kwang Kim ◽  
Gwan Beom Hwang ◽  
Seung Eun Lee

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.


2020 ◽  
Vol 53 (2) ◽  
pp. 8519-8524
Author(s):  
G. Hassan ◽  
A. Chemori ◽  
L. Chikh ◽  
P.E. Hervé ◽  
M. El Rafei ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document