scholarly journals Capacitance multiplier with large multiplication factor, high accuracy, and low power and silicon area for floating applications

2018 ◽  
Vol 15 (3) ◽  
pp. 20171191-20171191 ◽  
Author(s):  
Ivan Padilla-Cantoya ◽  
Luis Rizo-Dominguez ◽  
Jesus E. Molinar-Solis
2012 ◽  
Vol 184-185 ◽  
pp. 1613-1617
Author(s):  
Jin Fang Zhu

This article studies the embedded SPC and its application in roundness measuring system by analyzing the current roundness measurement principle and technology. With analyzing the process of data collection, date treatment and various kinds of tool graphic construction, we study the feasibility of integrating SPC into roundness measurement and finally apply the embedded SPC as pure software into roundness measuring system. We design the roundness measuring system based on embedded SPC and develop the roundness measuring system of low power consumption, high accuracy and easy application, which is suitable for industry field usage.


2021 ◽  
Author(s):  
Yi Wang ◽  
Cheng Li ◽  
Yingjie Yu ◽  
Su Huang
Keyword(s):  

2021 ◽  
Author(s):  
Siqi Yang ◽  
Jiajing Fan ◽  
Jiahao Liu ◽  
Liang Chang ◽  
Shuisheng Lin ◽  
...  

Author(s):  
Meng Fu ◽  
Stan Skafidas ◽  
Iven Mareels

This article describes how, in recent years, with the development of microelectronics, implantable electronic devices have been playing a significant role in modem medicine. Examples of such electronic implant devices are, for instance, retinal prosthesis and brain implants. It brings great challenges in low power radio frequency (RF) and analog designs. This article presents a low power Gaussian frequency shift keying (GFSK) demodulator designed for Medical Implant Communications Service (MICS) band Receiver. This demodulator utilizes a novel structure that a wide IF range can be handled and presents the smallest Δf/f ratio in any published GFSK demodulators. In theory the demodulation method can be applied to any RF frequency. The demodulator draws 550uA from a 1 V power supply. A maximum data rate of 400 Kbits/s can be achieved within the 300 KHz channel bandwidth defined by MICS. A simulated signal-to-noise ratio (SNR) of 15.2dB at AWGN channel is obtained to achieve 10-3 bit error rate (BER). This demodulator is fabricated on 65-nm CMOS and occupies 0.12mm2 silicon area.


2019 ◽  
Vol 29 (07) ◽  
pp. 2050109
Author(s):  
Yan Li ◽  
Yong Liang Li

A novel capacitance multiplier is proposed to implement an ultra-low-frequency filter for physiological signal processing in biomedical applications. With the proposed multiplier, a simple first-order low-pass filter achieves a [Formula: see text]3-dB frequency of 33.4[Formula: see text]μHz with a 1-pF capacitance and a 20[Formula: see text]k[Formula: see text] resistance. This corresponds to a multiplication factor of as large as [Formula: see text]. By changing the controlling terminal, the [Formula: see text]3-dB frequency can be tuned in a wide range of 33.4[Formula: see text]μHz–6.3[Formula: see text]kHz.


Author(s):  
Boqiang Wu ◽  
Nianxiong Tan ◽  
Shupeng Zhong ◽  
Changyou Men ◽  
Sufang Huang

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