Development of Test Structure for Variability Evaluation using Charge-Based Capacitance Measurement

2014 ◽  
Vol E97.C (11) ◽  
pp. 1117-1123 ◽  
Author(s):  
Katsuhiro TSUJI ◽  
Kazuo TERADA ◽  
Ryota KIKUCHI
Keyword(s):  
Test Structure ◽  
Capacitance Measurement

Back-End-of-Line Quadrature-Clocked Voltage-Dependent Capacitance Measurements

2009 ◽  
Author(s):  
Stas Polonsky ◽  
Paul Solomon ◽  
Mark Ketchen ◽  
Ernesto Shiling ◽  
Laertis Economikos ◽  
...  
Keyword(s):  
Chemical Mechanical Polishing ◽  
Measurement Techniques ◽  
Test Structure ◽  
Capacitance Measurement ◽  
Analog Design ◽  
Capacitance Measurements ◽  
Front End ◽  
Metal Pattern ◽  
Voltage Dependent ◽  
Dc Current

Abstract We compare different dc current-based integrated capacitance measurement techniques in terms of their applicability to modern CMOS technologies. The winning approach uses quadrature detection to measure mutual Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) capacitances. We describe our implementation of this approach, Quadrature-clocked Voltage-dependent Capacitance Measurements (QVCM), and its application to 45 nm node BEOL: wire capacitance variability measurements for analog design, and capacitive test structure to measure the effect of metal pattern density on Chemical-Mechanical Polishing (CMP) and Reactive Ion Etching (RIE).

Precise Localization of 28 nm via Chain Resistive Defect Using EBAC and Nanoprobing

2012 ◽  
Author(s):  
P. Larré ◽  
H. Tupin ◽  
C. Charles ◽  
R.H. Newton ◽  
A. Reverdy
Keyword(s):  
Electron Beam ◽  
Failure Analysis ◽  
Test Structure ◽  
Precise Localization ◽  
Isolation Method ◽  
Accurate Detection ◽  
Conventional Methods ◽  
Technology Nodes ◽  
Tem Lamella

Abstract As technology nodes continue to shrink, resistive opens have become increasingly difficult to detect using conventional methods such as AVC and PVC. The failure isolation method, Electron Beam Absorbed Current (EBAC) Imaging has recently become the preferred method in failure analysis labs for fast and highly accurate detection of resistive opens and shorts on a number of structures. This paper presents a case study using a two nanoprobe EBAC technique on a 28nm node test structure. This technique pinpointed the fail and allowed direct TEM lamella.

Backside FIB Device Modifications Through the BOX Layer of an SOI Device

2002 ◽  
Author(s):  
Jeffery P. Huynh ◽  
Joseph P. Shannon ◽  
Richard W. Johnson ◽  
Mike Santana ◽  
Thomas Y. Chu ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Oxide Layer ◽  
Cross Section ◽  
Test Structure ◽  
Ring Oscillator ◽  
Oscillator Circuit ◽  
Entire Process ◽  
Oscillator Frequency ◽  
Polysilicon Gate ◽  
Resistance Data

Abstract Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

2014 ◽  
Vol 35 (2) ◽  
pp. 178-180 ◽  
Author(s):  
Wenjie Lu ◽  
Alex Guo ◽  
Alon Vardi ◽  
Jesus A. del Alamo
Keyword(s):  
Ohmic Contacts ◽  
Test Structure ◽  
Nano Scale
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