scholarly journals MOS Current Mode Logic with Capacitive Coupling

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta

A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18 μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1156 ◽  
Author(s):  
Esteban Tlelo-Cuautle ◽  
Perla Rubi Castañeda-Aviña ◽  
Rodolfo Trejo-Guerra ◽  
Victor Hugo Carbajal-Gómez

The design of a wide-band voltage-controlled oscillator (VCO) modified as a VCO with programmable tail currents is introduced herein. The VCO is implemented by using CMOS current-mode logic stages, which are based on differential pairs that are connected in a ring topology. SPICE simulation results show that the VCO operates within the frequency ranges of 2.65–5.65 GHz, and when it is modified, the VCO with programmable tail currents operates between 1.38 GHz and 4.72 GHz. The design of the CMOS differential stage is detailed along with the symbolic approximation of its dominant pole, which is varied to increase the frequency response in order to achieve a higher oscillation frequency when implementing the ring oscillator structure. The layout of the VCO is described and pre- and post-layout simulations are provided, which are in good agreement using CMOS technology of 180 nm. Finally, process, voltage and temperature variations are performed to guarantee robustness of the designed CMOS ring oscillator.


2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta

Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented.


1990 ◽  
Vol 01 (01) ◽  
pp. 101-124 ◽  
Author(s):  
P.K. TIEN

The needs for multi-gigabits/second digital electronics in advanced lightwave systems have motivated R & D for the next generation of high speed bipolar technology. The speed of the digital circuit may be estimated from the propagation delay of the logic gate. We discuss physics of the delay and show that it is fundamentally limited by the time needed for turning on (off) a transistor and by the time for charging (discharging) of capacitances in the circuit. We present a large-signal theory based on a charge-control model for the calculation of these limits. The results obtained for emitter coupled logic and current mode logic are used to analyze current technologies of silicon bipolar and GaAs HBTs.


Sensors ◽  
2020 ◽  
Vol 20 (16) ◽  
pp. 4612 ◽  
Author(s):  
Danilo Monda ◽  
Gabriele Ciarpi ◽  
Sergio Saponara

This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and Single Event Effect simulations results, performed with a double exponential current pulses generator, are presented in detail for both VCOs. Although the RO-VCO performances in terms of technology scaling and high-integration density were attractive, the simulations on the process variations demonstrated its inability to generate the target frequency in harsh operating conditions. Instead, the LC-VCO highlighted a lower influence through Process-Voltage-Temperature simulations on the oscillation frequency. Both architectures were biased with a supply voltage of 1.2 V. The achieved results for the second architecture analyzed were attractive to address the requirements of the new SpaceFibre aerospace standard.


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