Design of MOS Current Mode Logic Gates – Computing the Limits of Voltage Swing and Bias Current

2005 ◽  
Author(s):  
G. Caruso
Keyword(s):  
Logic Gates ◽  
Current Mode ◽  
Bias Current ◽  
Current Mode Logic ◽  
Voltage Swing

scholarly journals MOS Current Mode Logic with Capacitive Coupling

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
Analytical Model ◽  
Digital Circuits ◽  
Logic Gates ◽  
Current Mode ◽  
Cmos Technology ◽  
Capacitive Coupling ◽  
Ring Oscillator ◽  
Switching Speed ◽  
Current Mode Logic

A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18 μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.

scholarly journals MCML D-Latch Using Triple-Tail Cells: Analysis and Design

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
High Speed ◽  
Analytical Modeling ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Power Efficient ◽  
Analysis And Design ◽  
Current Mode Logic ◽  
Voltage Swing

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.

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