scholarly journals Multioutput Flyback DC-DC Converter for MIL Applications

2021 ◽  
Author(s):  
Sukumar Patil ◽  
Bhanuprakash CV ◽  
Bhoopendrakumar Singh
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Short Circuit ◽  
Current Mode ◽  
Switching Frequency ◽  
Current Output ◽  
Military Applications ◽  
Input Range ◽  
Emi Filter ◽  
Load Conditions

Abstract This paperwork explains the design and development of isolated triple output dc-dc converter for military applications. Converter has designed with flyback topology with opto-coupler based feedback for regulated main output and regulators are used to provide another two outputs. It is realized with switching frequency of 190KHz (internal free run frequency) and can be able to operate up to 210KHz with external synchronization. LTM46xx micro-modules are used as buck regulators to provide required lower output voltages. Current mode pulse width modulation controller IC is used to drive the MOSFET switch. It has following features like inbuilt EMI filter, external inhibit function, external synchronization capability, input under voltage and over voltage protection, primary side over current, output over current and short circuit protection. Converter is designed to operate for wide input range from 18V to 36V with efficiency of more than 75% in full load conditions.

scholarly journals Mitigating the dead-time effects on harmonics spectrum of inverter waveform by the confined band VSFPWM technique

2021 ◽  
Vol 12 (1) ◽  
pp. 295
Author(s):  
Hussain Attia ◽  
Hang Seng Che ◽  
Tan Kheng Suan Freddy ◽  
Ahmad Elkhateb
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Short Circuit ◽  
Harmonic Distortion ◽  
Switching Frequency ◽  
Positive Effects ◽  
The Dead ◽  
The Impact ◽  
Low Order

The dead-time is necessary to be inserted between the gates drive pulses of the two power electronic switches in a one leg of any inverter to avoid a short circuit in the leg and the DC supply as well. However, adding the dead-time increases the low order harmonics of the output voltage/current waveform of the inverter. This paper investigates the positive effects of decreasing the pulse width modulation (PWM) drive pulses number per fundamental period on the current low order harmonics. In addition, this paper evaluates the impact of the confined band variable switching frequency pulse width modulation (CB-VSFPWM) technique on inverter performance in terms of dead-time mitigating, and consequenctely lowering the low order harmonics. CB-VSFPWM technique reduces the total harmonic distortion (THD) levels in the inverter output current as well. Theoretical analysis of the CB-VSFPWM effectiveness in reducing the negative effect of the dead-time has explained in this study and confirmed by the MATLAB/Simulink simulation results.

A Novel Soft Switching Based Fuzzy Logic Control for Single Phase Inverter

2014 ◽  
Vol 573 ◽  
pp. 143-149
Author(s):  
N. Ismayil Kani ◽  
B.V. Manikandan ◽  
Prabakar Perciyal
Keyword(s):  
Fuzzy Logic ◽  
Pulse Width ◽  
Pulse Width Modulation ◽  
Soft Switching ◽  
Switching Frequency ◽  
Pwm Inverter ◽  
Zero Voltage Switching ◽  
Control Scheme ◽  
Zero Voltage ◽  
Voltage Switching

—This The Pulse Width Modulation (PWM) DC-to-AC inverter has been widely used in many applications due to its circuit simplicity and rugged control scheme. It is however driven by a hard-switching pulse width modulation (PWM) inverter, which has low switching frequency, high switching loss, high electro-magnetic interference (EMI), high acoustic noise and low efficiency, etc. To solve these problems of the hard-switching inverter, many soft-switching inverters have been designed in the past. Unfortunately, high device voltage stress, large dc link voltage ripples, complex control scheme and so on are noticed in the existing soft-switching inverters. This proposed work overcomes the above problems with simple circuit topology and all switches work in zero-voltage switching condition. Comparative analysis between conventional open loop, PI and fuzzy logic based soft switching inverter is also presented and discussed. Keywords—Zero voltage switching, Inverter, Dc link, PI controller, Fuzzy logic system control ,Modulation strategy, Soft switching

scholarly journals A Novel Filter Extracted Equivalent Control Based Fixed Frequency Sliding Mode Approach for Power Electronic Converters

Energies ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 853 ◽  
Author(s):  
Abdul Yasin ◽  
Muhammad Ashraf ◽  
Aamer Bhatti
Keyword(s):  
Boundary Layer ◽  
Pulse Width ◽  
Pulse Width Modulation ◽  
Sliding Mode ◽  
Discontinuous Function ◽  
Switching Frequency ◽  
Power Electronic ◽  
Power Electronic Converters ◽  
Fixed Frequency ◽  
Equivalent Control

The key issue in the implementation of the Sliding Mode Control (SMC) in analogue circuits and power electronic converters is its variable switching frequency. The drifting frequency causes electromagnetic compatibility issues and also adversely affect the efficiency of the converter, because the proper size of the inductor and the capacitor depends upon the switching frequency. Pulse Width Modulation based SMC (PWM-SMC) offers the solution, however, it uses either boundary layer approach or employs pulse width modulation of the ideal equivalent control signal. The first technique compromises the performance within the boundary layer, while the latter may not possess properties like robustness and order reduction due to the absence of the discontinuous function. In this research, a novel approach to fix the switching frequency in SMC is proposed, that employs a low pass filter to extract the equivalent control from the discontinuous function, such that the performance and robustness remains intact. To benchmark the experimental observations, a comparison with existing double integral type PWM-SMC is also presented. The results confirm that an improvement of 20% in the rise time and 25.3% in the settling time is obtained. The voltage sag during step change in load is reduced to 42.86%, indicating the increase in the robustness. The experiments prove the hypothesis that a discontinuous function based fixed frequency SMC performs better in terms of disturbances rejection as compared to its counterpart based solely on ideal equivalent control.

scholarly journals A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2195
Author(s):  
Jin-Wook Kang ◽  
Seung-Wook Hyun ◽  
Yong Kan ◽  
Hoon Lee ◽  
Jung-Hyo Lee
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Short Circuit ◽  
Reference Voltage ◽  
Voltage Source ◽  
Switching Operation ◽  
Voltage Unbalance ◽  
Offset Voltage ◽  
Simulation And Experiment

This paper proposes a novel pulse width modulation (PWM) for a three-level neutral point clamped (NPC) voltage source inverter (VSI). When the conventional PWM method is used in three-level NPC VSI, dead time is required to prevent a short circuit caused by the operation of complementary devices on the upper and lower arms. However, current distortion is increased because of the dead time and it can also cause a voltage unbalance in the dc-link. To solve this problem, we propose a zero dead-time width modulation (ZDPWM) which does not require dead time used in complementary operation. The proposed technique applies the offset voltage to the space vector pulse width modulation (SVPWM) reference voltage for the same modulation index (MI) as the conventional SVPWM, but any complementary switching operation needs dead time. In addition, the proposed method is divided into four operation sections using the reference voltage and phase current to operate switching devices which flow the current depending on the section. This ZDPWM method is simply implemented by carrier and reference voltage that reduce the current distortion, because complementary operation that needs dead time is not implemented. However, the operation section is delayed due to the sampling delay that occurs during the experiment. Therefore, in this paper, we conduct a modeling of sampling delay to improve the delay of operation section. To verify the principle and feasibility of the proposed ZDPWM method, a simulation and experiment are implemented.

Synchronized Symmetrical Bus-Clamping PWM Strategies for Three Level Inverter: Applications to Low Switching Frequencies

2011 ◽  
Vol 12 (2) ◽  
Author(s):  
Sreenivasappa Bhupasandra Veeranna ◽  
Udaykumar R Yaragatti ◽  
Abdul R Beig
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
High Performance ◽  
Pulse Width Modulation ◽  
Industrial Applications ◽  
Voltage Source ◽  
Switching Frequency ◽  
Space Vector ◽  
Digital Implementation ◽  
Switching Losses

The digital control of three-level voltage source inverter fed high power high performance ac drives has recently become a popular in industrial applications. In order to control such drives, the pulse width modulation algorithm needs to be implemented in the controller. In this paper, synchronized symmetrical bus-clamping pulse width modulation strategies are presented. These strategies have some practical advantages such as reduced average switching frequency, easy digital implementation, reduced switching losses and improved output voltage quality compared to conventional space vector pulse width modulation strategies. The operation of three level inverter in linear region is extended to overmodulation region. The performance is analyzed in terms THD and fundamental output voltage waveforms and is compared with conventional space vector PWM strategies and found that switching losses can be minimized using bus-clamping strategy compared to conventional space vector strategy. The proposed method is implemented using Motorola Power PC 8240 processor and verified on a constant v/f induction motor drive fed from IGBT based inverter.

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