scholarly journals Field effect transistor to enable registration of reaction energy pathways

2020 ◽  
Author(s):  
Alexander E. Kuznetsov ◽  
Mariia S. Andrianova ◽  
Evgeniy V. Kuznetsov

Abstract Each chemical reaction has its own energy profile that represents the energy changes during the transformation of reactants into products. Together with other sources, it provides information about the reaction mechanism. Here, we show how a complementary metal-oxide-semiconductor (CMOS)–compatible field effect transistor can be used to register an energy pathway of a chemical reaction. As a proof of concept we record an energy profiles (energy changes vs. reaction coordinate) of 3,3′,5,5′-tetramethylbenzidine oxidation catalyzed by horseradish peroxidase. This approach can be potentially extended to study other enzymatic and non-enzymatic reactions.

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.


2021 ◽  
Author(s):  
Kamal Y. Kamal ◽  
Radu Muresan ◽  
Arafat Al-Dweik

<p>This article reviews complementary metal-oxide-semiconductor (CMOS) based physically unclonable functions (PUFs) in terms of types, structures, metrics, and challenges. The article reviews and classifies the most basic PUF types. The article reviews the basic variations originated during a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process. Random <a>variations</a> at transistor level lead to acquiring unique properties for electronic chips. These variations help a PUF system to generate a unique response. This article discusses various concepts which allow for more variations at CMOS technology, layout, masking, and design levels. It also discusses various PUF related topics.</p>


1998 ◽  
Vol 37 (Part 1, No. 11) ◽  
pp. 5926-5931
Author(s):  
Masahiro Shimizu ◽  
Takashi Kuroi ◽  
Masahide Inuishi ◽  
Hideaki Arima ◽  
Haruhiko Abe ◽  
...  

2021 ◽  
Author(s):  
Kamal Y. Kamal ◽  
Radu Muresan ◽  
Arafat Al-Dweik

<p>This article reviews complementary metal-oxide-semiconductor (CMOS) based physically unclonable functions (PUFs) in terms of types, structures, metrics, and challenges. The article reviews and classifies the most basic PUF types. The article reviews the basic variations originated during a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process. Random <a>variations</a> at transistor level lead to acquiring unique properties for electronic chips. These variations help a PUF system to generate a unique response. This article discusses various concepts which allow for more variations at CMOS technology, layout, masking, and design levels. It also discusses various PUF related topics.</p>


Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1303
Author(s):  
Hoontaek Lee ◽  
Junsoo Kim ◽  
Kumjae Shin ◽  
Wonkyu Moon

We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The - characteristics of the inbuilt MOSFET reflect the design and fabrication modifications, and measurement of a buried electrode revealed improved ToGoFET imaging performance. The minimum measurable value was enhanced 20-fold.


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