scholarly journals Design of Low Power Neuro-amplifier Circuit with Miller Compensation Technique for Biomedical Neuro-implantable Devices

2021 ◽  
Author(s):  
Kriti Dwivedi ◽  
Aparna Gupta ◽  
Ritika Oberoi ◽  
Ribu Mathew
Keyword(s):  
Work Performance ◽  
Implantable Devices ◽  
Simulation Software ◽  
Amplifier Circuit ◽  
Circuit Performance ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Compensation Technique ◽  
Amplifier Design ◽  
Feedback Techniques

Neuro-amplifiers form an integral part of biomedical implantable devices. In this paper, we design a neuro-amplifier circuit with Miller compensation capacitor. The neuro-amplifier design is based on operational transconductance amplifier (OTA) with an active load. In this work, performance of the neuro-amplifier is enhanced by incorporating the Miller compensation technique. Design and simulation of the neuro-amplifier circuit is performed using SPICE simulation software. Body biasing and feedback techniques are imparted to optimize the circuit performance. Simulation results show that the neuro-amplifier circuit has a mid-frequency gain and 3-dB bandwidth of 48dB, and 16kHzrespectively.

From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design

2016 ◽  
Vol 6 (4) ◽  
pp. 187
Author(s):  
Rodrigo Alves De Lima Moreto ◽  
Antonio Luis Pacheco Rotondaro ◽  
Carlos Eduardo Thomaz ◽  
Salvador Pinillos Gimenez
Keyword(s):  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier ◽  
Amplifier Design

scholarly journals FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Ravindra Singh Kushwah ◽  
Shyam Akashe
Keyword(s):  
Analog Circuits ◽  
High Performance ◽  
Analog Circuit ◽  
Schmitt Trigger ◽  
Low Noise ◽  
Operational Transconductance Amplifier ◽  
Back Gate ◽  
Amplifier Circuit ◽  
Tunable Circuits ◽  
Transconductance Amplifier

We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability, resulting relatively high Ion/Ioff ratio. In this paper, we proposed a tunable analog circuit such as CMOS amplifier circuit, Schmitt trigger circuit, and operational transconductance amplifier circuit, these circuit blocks are necessary for low noise high performance ICs for analog applications. Gain, phase, group delay, and output response of analog tunable circuits have been discussed in this paper. The proposed FinFET based analog tunable circuits have been designed using Cadence Virtuoso tool at 45 nm.

scholarly journals Efficient technique for ultra broadband, linear power amplifier design

2012 ◽  
Vol 4 (6) ◽  
pp. 559-567 ◽  
Author(s):  
Ahmed Sayed ◽  
Sebastian Preis ◽  
Georg Boeck
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Impedance Matching ◽  
Network Synthesis ◽  
Circuit Performance ◽  
Power Added Efficiency ◽  
Starting Point ◽  
Saturated Output Power ◽  
Linear Power Amplifier ◽  
Amplifier Design

In this paper, a 10 W ultra-broadband GaN power amplifier (PA) is designed, fabricated, and tested. The suggested design technique provides a more accurate starting point for matching network synthesis and better prediction of achievable circuit performance. A negative-image model was used to fit the extracted optimum impedances based on source-/load-pull technique and multi-section impedance matching networks were designed. The implemented amplifier presents an excellent broadband performance, resulting in a gain of 8.5 ± 0.5 dB, saturated output power of ≥10 W, and power added efficiency (PAE) of ≥23% over the whole bandwidth. The linearity performance has also been characterized. An output third-order intercept point (OIP3) of ≥45 dBm was extracted based on a two-tone measurement technique in the operating bandwidth with different frequency spacing values. The memory effect based on AM/AM and AM/PM conversions was also characterized using a modulated WiMAX signal of 10 MHz bandwidth at 5.8 GHz. Furthermore, a broadband Wilkinson combiner was designed for the same bandwidth with very low loss to extend the overall output power. Excellent agreement between simulated and measured PA performances was also achieved.

scholarly journals Raman amplifier design using geometry compensation technique

2004 ◽  
Vol 12 (3) ◽  
pp. 436 ◽  
Author(s):  
Zhaohui Li ◽  
Chao Lu ◽  
Jian Chen ◽  
Chunliu Zhao
Keyword(s):  
Raman Amplifier ◽  
Compensation Technique ◽  
Amplifier Design

scholarly journals Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology

2019 ◽  
Vol 23 (2) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Eklare Akshay Vijaykumar ◽  
Prabir Saha
Keyword(s):  
Graphical Models ◽  
Cmos Technology ◽  
Single Stage ◽  
Silicon On Insulator ◽  
Short Channel ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Channel Effects ◽  
Performance Specifications ◽  
Amplifier Design

The downscaling of complementary metal-oxidesemiconductor (CMOS) technology is approaching its limits imposed by short-channel effects (SCE), thereby multi-gate MOSFETs have been proposed to extend the scalability. Ultrathin-body silicon-on-insulator (UTBSOI) transistor is one of the dual-gated devices which offers better immunity towards SCEs. In this paper, two designs have been proposed for single-stage operational transconductance amplifiers (OTA) using the CMOS and UTBSOI. The CMOS based OTA (CMOS-OTA) has been designed where sizing (W/L) of the constituting MOSFETs have been evaluated through gm/Id methodology and the same OTA topology has been simulated using UTBSOI (UTBSOI-OTA) considering the same W/L. The DC simulation is carried out over the BSIM3v3 model to store the operating point parameters in the form of graphical models. The mathematical expressions for performance specifications have been applied over the graphical models to evaluate the required W/L. Individual comparisons between the two proposed designs have also been carried out for further applications. Based on simulation results at the schematic level, the UTBSOI-OTA has higher DC gain of 33.26% and lesser power consumption of 2.81% over the CMOS-OTA. Moreover, comparative analysis of performance parameters like DC gain and common-mode rejection ratio (CMRR), have been compared with the best-reported paper so far. In addition to this, the UTBSOI-OTA has been applied to practical integrator circuits for further verification.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

2020 ◽  
Vol 48 (11) ◽  
pp. 1990-2005 ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Frequency Response ◽  
Double Pole ◽  
Miller Compensation ◽  
Compensation Technique
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