scholarly journals Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology

2019 ◽  
Vol 23 (2) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Eklare Akshay Vijaykumar ◽  
Prabir Saha
Keyword(s):  
Graphical Models ◽  
Cmos Technology ◽  
Single Stage ◽  
Silicon On Insulator ◽  
Short Channel ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Channel Effects ◽  
Performance Specifications ◽  
Amplifier Design

The downscaling of complementary metal-oxidesemiconductor (CMOS) technology is approaching its limits imposed by short-channel effects (SCE), thereby multi-gate MOSFETs have been proposed to extend the scalability. Ultrathin-body silicon-on-insulator (UTBSOI) transistor is one of the dual-gated devices which offers better immunity towards SCEs. In this paper, two designs have been proposed for single-stage operational transconductance amplifiers (OTA) using the CMOS and UTBSOI. The CMOS based OTA (CMOS-OTA) has been designed where sizing (W/L) of the constituting MOSFETs have been evaluated through gm/Id methodology and the same OTA topology has been simulated using UTBSOI (UTBSOI-OTA) considering the same W/L. The DC simulation is carried out over the BSIM3v3 model to store the operating point parameters in the form of graphical models. The mathematical expressions for performance specifications have been applied over the graphical models to evaluate the required W/L. Individual comparisons between the two proposed designs have also been carried out for further applications. Based on simulation results at the schematic level, the UTBSOI-OTA has higher DC gain of 33.26% and lesser power consumption of 2.81% over the CMOS-OTA. Moreover, comparative analysis of performance parameters like DC gain and common-mode rejection ratio (CMRR), have been compared with the best-reported paper so far. In addition to this, the UTBSOI-OTA has been applied to practical integrator circuits for further verification.

Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

2011 ◽  
Vol 110-116 ◽  
pp. 5150-5154
Author(s):  
K. Senthil Kumar ◽  
Saptarsi Ghosh ◽  
Anup Sarkar ◽  
S. Bhattacharya ◽  
Subir Kumar Sarkar
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Cmos Technology ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Silicon Bulk ◽  
Channel Effects

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Comparative study of symmetrical OTA performance in 180 nm, 130 nm and 90 nm CMOS technology

2019 ◽  
Vol 14 (1) ◽  
pp. 230
Author(s):  
Wan Mohammad Ehsan Aiman Bin Wan Jusoh ◽  
Siti Hawa Ruslan ◽  
Nabihah Ahmad ◽  
Warsuzarina Mat Jubadi ◽  
Rahmat Sanudin
Keyword(s):  
Comparative Study ◽  
Detection System ◽  
Cmos Technology ◽  
Common Mode ◽  
Voltage Supply ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
High Cmrr ◽  
The Comparative Study ◽  
Electrocardiogram Ecg

<span>In this paper, the comparative study of symmetrical Operational Transconductance Amplifier (OTA) performance between 180 nm, 130 nm and 90 nm CMOS technology have been done thoroughly to find the relationship between voltage supply and bias current with performance parameters (gain, power consumption and Common-Mode Rejection Ratio (CMRR)). The OTA which adopts symmetrical topology is designed carefully and simulated using Synopsys HSpice software and the results are carefully analyzed and compared. The symmetrical OTA designed in 90 nm CMOS technology is found to be the best because the power consumed is only 9.83 µW from ±0.9 V voltage supply and the OTA achieved 55.9 dB of the DC gain. The CMRR of the symmetrical 90 nm OTA is 140 dB which is sufficient to reject the common-mode signals in electrocardiogram (ECG) input signal. The symmetrical 90 nm OTA is suitable to be implemented as bioamplifier in ECG signal detection system as it consumed low power and has a high CMRR characteristic.</span>

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

2013 ◽  
Vol 411-414 ◽  
pp. 1645-1648
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Jian Gang Shi ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Current Mirror ◽  
Slew Rate ◽  
Operational Transconductance Amplifier ◽  
Theory Analysis ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Simulation Results

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

scholarly journals Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

2013 ◽  
Vol 2013 ◽  
pp. 1-8
Author(s):  
Vandna Sikarwar ◽  
Saurabh Khandelwal ◽  
Shyam Akashe
Keyword(s):  
Research Work ◽  
Random Access ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Short Channel ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Sram Cell ◽  
Channel Effects ◽  
Independent Gate

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

Molybdenum as a Gate Electrode for Deep Sub-Micron CMOS Technology

2000 ◽  
Vol 611 ◽  
Author(s):  
Pushkar Ranade ◽  
Yee-Chia Yeo ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
...  
Keyword(s):  
Work Function ◽  
Elevated Temperatures ◽  
Coefficient Of Thermal Expansion ◽  
Cmos Technology ◽  
Gate Electrode ◽  
Short Channel ◽  
Gate Electrodes ◽  
Channel Effects ◽  
Work Functions ◽  
Gate Resistance

ABSTRACTMolybdenum has several properties that make it attractive as a CMOS gate electrode material. The high melting point (∼2610°C) and low coefficient of thermal expansion (5×10−6/°C, at 20 °C) are well suited to withstand the thermal processing budgets normally encountered in a CMOS fabrication process. Mo is among the most conductive refractory metals and provides a significant reduction in gate resistance as compared with doped polysilicon. Mo is also stable in contact with SiO2 at elevated temperatures. In order to minimize short-channel effects in bulk CMOS devices, the gate electrodes must have work functions that correspond to Ec (NMOS) and Ev (PMOS) in Si. This would normally require the use of two metals with work functions differing by about 1V on the same wafer and introduce complexities associated with selective deposition and/or etching. In this paper, the dependence of the work function of Mo on deposition and annealing conditions is investigated. Preliminary results indicate that the work function of Mo can be varied over the range of 4.0-5.0V by a combination of suitable post-deposition implantation and annealing schemes. Mo is thus a promising candidate to replace polysilicon gates in deep sub-micron CMOS technology. Processing sequences which might allow the work function of Mo to be stabilized on either end of the Si energy band gap are explored.

scholarly journals Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation

2021 ◽  
Author(s):  
Mrinmoy Goswami ◽  
Ankush Chattopadhyay ◽  
Chayanika Bose
Keyword(s):  
Surface Potential ◽  
Drain Current ◽  
Silicon On Insulator ◽  
Short Channel ◽  
Accumulation Mode ◽  
Physical Constraints ◽  
High K ◽  
Channel Effects ◽  
High K Dielectric ◽  
Dual Material

Abstract The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. The device is also simulated using Silvaco device simulator. Both the analytical and simulation results are compared and found to match closely. Quasi 3-D modeling approach is adopted here to determine the surface potential of the above device. In this technique, the entire 3-D device is segregated into two 2-D devices with certain physical constraints. These 2-D devices are then analyzed separately to obtain the surface potentials, which are added together using suitable multiplication factors to get the surface potential of the 3-D device. This surface potential is, in turn, used to model the threshold voltage, sub-threshold drain current ( I d,sub ) and the drain induced barrier lowering (DIBL). The proposed device configuration reduces the I OFF significantly and offers excellent immunity to SCEs. The response of the proposed device is studied for the variations of certain device parameters, such as, thickness of High- K dielectric layer in stack gate, channel doping, and the workfunctions as well as lengths of the gate metals. Such study will lead to turn the proposed device immune to short channel effects through proper choice of various parameters.

scholarly journals Design of Low Power Less Leakage Quarternary Adder Using CMOS

2021 ◽  
pp. 110-121
Author(s):  
M. Sutha ◽  
Dr. R. Nirmala ◽  
Dr. E. Kamalavathi
Keyword(s):  
Low Power ◽  
Impact Ionization ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Surface Scattering ◽  
Short Channel Effects ◽  
Short Channel ◽  
Mos Devices ◽  
Channel Effects ◽  
Quaternary Adder

In VLSI, design and implementation of circuits with MOS devices and binary logic are quite usual. The Main Objective is to design a low power and minimum leakage Quaternary adder. The VLSI field consists of Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL). The Failures such as Short Channel Effects (SCE) Impact-ionization and surface scattering are in normalized aspects. The Quaternary radix on MVL (multi-valued logic) monitors and reduces the area. The Quaternary (four-valued) logic converts the quaternary signals and binary signals produced by the by the existing binary circuits. The Proposed is carried out with LTSPICE tool and CMOS technology.

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