scholarly journals Управление фрактальностью и размером серебряных кластеров при одностадийном синтезе гетероструктур Ag-ZnO

Author(s):  
Н.Д Якушова ◽  
И.А Аверин ◽  
И.А Пронин ◽  
А.А Карманов ◽  
Е.А. Алимова ◽  
...  

In the framework of a sol-gel technology we have been developed the joint and simultaneous synthesis of fractal silver nano- and microclusters and a matrix of ZnO metal oxide semiconductor material. We have demonstrated the possibility of flexible control of the size and fractal dimension of metal structures by changing the concentration of silver nitrate in the initial sol. The proposed approaches can be used in the manufacture of photocatalysts, thermistors, biosensors, as well as other instruments and devices of nano- and microsystem technology.

2012 ◽  
Vol 26 (31) ◽  
pp. 1250191 ◽  
Author(s):  
ALI BAHARI ◽  
REZA GHOLIPUR

To investigate characterization of Zr x La 1-x O y nanocrystallites as a buffer oxide in forming the metal-oxide-semiconductor field effect transistors (MOSFETs) structure, we synthesized Zr x La 1-x O y nanocrystallites by sol–gel method. Moreover, from the solution prepared, thin films on silicon wafer substrates have been realized by "dip-coating" with a pulling out speed of 5 cm min -1. The structure, morphology, electrical properties of thin film was examined by X-ray diffraction (XRD), scanning electron microscopy (SEM), atomic force microscopy (AFM) and transmission electron microscopy (TEM) techniques. Electrical property characterization was performed with metal-oxide-semiconductor (MOS) structures through capacitance–voltage (C–V) and current density–voltage (J–V) measurements. The leakage current density was below 1.0 ×10-6 A/cm 2 at 1 MV/cm.


2018 ◽  
Vol 7 (3) ◽  
pp. 267-282 ◽  
Author(s):  
Susmita Das ◽  
Vimal Chandra Srivastava

Abstract In the field of environmental science, metal oxide nanocomposites have gained a great attention for both theoretical and experimental aspects of their upgradation because of their wide range of practical applications such as catalysts, sensors, hydrogen storages, and optoelectronics. Among all nanocomposites, Copper oxide-zinc oxide (CuO-ZnO) has attracted more research due to their excellent tunable catalytic, electrical, optical, and magnetic properties and environment-friendly nature. Coupling of one metal oxide semiconductor with another metal oxide semiconductor produces an enlarged surface area, which provide more reactive sites, promotes mass transfer, promotes electron transfer, and avoids photo-corrosion of nanocomposites, which enhances its efficiency. The CuO-ZnO nanocomposite has been prepared by various methods such as co-precipitation, sol-gel, wet impregnation, and thermal decomposition. Depending on the preparation method and conditions used, different types of CuO-ZnO nanocomposites like Cu-doped ZnO, Cu supported/impregnated on ZnO, and CuO-ZnO mixed oxides with different morphologies of CuO-ZnO nanocomposites have been obtained. This article reviews the synthesis techniques of the CuO-ZnO nanocomposite and its morphology. Various practical applications of the CuO-ZnO nanocomposites have also been discussed.


Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.


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