Simulation Analysis of Circuit and Designing of PCB Layout of a CMOS based NOR Logic Gate using Open-Source Software eSim

Abstract: There are various basic gates like NAND, NOR gates which are extensively used in the designing of the more complex circuits with use higher number of transistors such as MUXs, ADCs and any other circuits. In this paper, we have carried out the modelling of NOR gate at 130 nm technology, yet maintaining comparable performance than conventional CMOS NOR gate logic structure. The modelling includes schematics design and PCB layout design run of the above gates. Also, the simulation results of the gates are obtained at the same node with start time, step time, stop time, rise time, fall time and delay and power dissipation. In this all process have been carried out of a CMOS based NOR Logic Gate using Open-Source Software eSim. Keywords: Simulation, PCB, NOR, CMOS, eSim

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Simulation Analysis of Circuit and Designing of PCB Layout of a CMOS based NAND Logic Gate using Open-Source Software eSim

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2021.37128 ◽

2021 ◽

Vol 9 (VII) ◽

pp. 3972-3977

Author(s):

Vanshika Tanwar

Keyword(s):

Open Source Software ◽

Simulation Analysis ◽

Logic Gate ◽

Logic Gates ◽

Building Blocks ◽

Simulation Software ◽

Nand Gate ◽

Different Types ◽

Simple Language ◽

Pcb Layout

A real world signals are mostly based on Boolean operators. In simple language Boolean operators are logic gates and logic gates are the building blocks of any circuit. There are different types of logic gates like AND, OR, NOT, NAND, NOR, XOR, and XNOR. These all-logic gates are implemented using a Boolean function. And all these logic gates internally are implemented using diodes and transistors. And when we implement all these logic gates using transistor and diodes then it comes under logic families. In this paper we are going to do the analysis of NAND GATE using CMOS in 180 nm technology and has also designed its PCB layout. We are going to carried out the whole simulation of the proposed design of NAND Gate in eSim (Electronic Simulation) Software which is an EDA tool. And by changing the different values of inputs of NAND Gate we are observing respective output in simulation process of eSim.

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Function Expansion of a Chaotic Logic Unit

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.171-172.283 ◽

2010 ◽

Vol 171-172 ◽

pp. 283-287

Author(s):

Yi Yan Sheng ◽

Wen Bo Liu

Keyword(s):

Numerical Model ◽

Circuit Design ◽

Simulation Analysis ◽

Circuit Simulation ◽

Logic Gate ◽

Logic Gates ◽

Control Voltage ◽

Computing Unit ◽

Nor Gate ◽

The Impact

Chaos computing is a new circuit design scheme of using chaos computing units to achieve reconfigurable logic gates. The computing unit can function as different kinds of logic gates by changing external parameters. In this paper, the possibilities of expanding the function of a chaotic NOR gate proposed in the literature is studied. The numerical model for the circuit design was built by constructing differential equations fit for Matlab integration mechanism. Besides, numerical model for integrator saturation was built to make results of numerical simulation conform to that of circuit simulation. Analysis of the impact of integrator saturation was done. With the analysis and by changing the control voltage, NAND function was expanded for the original chaotic logic gate that was only able to function as a NOR gate. By adding the function control signal to the input end and setting the voltage of it to different levels, the computing unit becomes a real time reconfigurable one.

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Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

10.21203/rs.3.rs-392266/v1 ◽

2021 ◽

Author(s):

Lokesh B ◽

Sai Pavan kumar K ◽

Pown M ◽

Lakshmi B

Keyword(s):

Power Consumption ◽

Logic Gate ◽

Logic Gates ◽

Propagation Delay ◽

Logic Circuits ◽

Logic Circuit ◽

Nand Gate ◽

Double Gate ◽

Nor Gate ◽

Nor Logic Gate

Abstract This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit

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Computation of backwater effects in low lying (marshland) catchments – a re-usable and efficient method in an open source hydrological model

10.5194/egusphere-egu21-11714 ◽

2021 ◽

Author(s):

Sandra Hellmers ◽

Christoph Sauer ◽

Peter Fröhle

Keyword(s):

Numerical Modelling ◽

Open Source ◽

Real Time ◽

Open Source Software ◽

Efficient Method ◽

Hydrological Model ◽

Flood Routing ◽

Data Availability ◽

Time Step ◽

Numerical Approaches

An efficient method to solve a significant weakness in hydrological modelling to compute backwater effects in low lying catchments is presented. The re-usable and transferable method is implemented in the open source software KalypsoNA (KalypsoHydrology) and validated with results of a tidal influenced low lying catchment study.&#160; Especially in low lying (marshy) catchments, the pressure on current storm water drainage systems raises due to combined impacts of enlarged urbanisation on the one hand and mean sea level rise and heavy storm events on the other hand. Models are applied to analyse and assess the resulting consequences by these impacts on the flood routing along a stream using different hydrological approaches: (i) pure black box (namely empirical, lumped), (ii) hydrological conceptual or (iii) hydrodynamic-numerical approaches. The computation of &#64258;ow depths, velocities and backwater effects in streams as well as on forelands are not yet modelled with hydrological approaches, but using simplified hydrodynamic-numerical approaches. A requirement for accurate hydrodynamic-numerical modelling is high resolution data of the topography of the main channel and the &#64258;ood plain in case of bank over&#64258;ow. Hence, the availability of suitable detailed pro&#64257;le data from measurements is crucial for hydrodynamic-numerical modelling. The comparatively long computing time for hydrodynamic-numerical model simulations is no limitation for answering special research questions, but it poses a limitation in real-time operational application and for meso to regional scale catchment modelling (>100 km2).&#160; To resolve the shortcomings in hydrological approaches to model water depths and backwater effects, new concepts are required which are applicable for catchments with scarce data availability, efficient for real-time operational model application, open for further model developments and re-useable for other hydrological model implementations. This contribution presents the development, implementation and evaluation of a method for modelling backwater effects based on a hydrological &#64258;ood routing approach and a backwater volume routing according to the water level slope. The developed method computes the backwater effects in two steps. First, the in&#64258;ow from sub-catchments and the non-backwater affected &#64258;ood routing processes are computed. Secondly, the afflux conditions are calculated which cause backwater effects in upstream direction. Afflux conditions occur mainly at tributary inlets or control structures (for example, tide gates, weirs, retention ponds or sluices). The input parameters comprise simplified or complex geometrical data per stream segment. Therefore, the model is applicable for catchments with a good or scarce availability of data. Computation time is in the range of max 3 minutes even for large catchments (> 150 km&#178; with several sub- and sub-sub-catchments) using a time step size of 15 minutes for a 14 days simulation and is therefore applicable for real-time operational simulations in flood forecasting.&#160; The proposed method is re-useable and transferable to other hydrological numerical models which use conceptual hydrological flood routing approaches (e.g. Muskingum-Cunge or Kalinin-Miljukov). The open source software model KalypsoHydrology and the calculation core KalypsoNA are available at https://sourceforge.net/projects/kalypso/ and http://kalypso.wb.tu-harburg.de/downloads/. Open access for developments and user application is supported by an online accessible commitment management via SourceForge and a wiki as an online manual.

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