scholarly journals Scaling function based on Chinese remainder theorem applied to a recursive filter design

2014 ◽  
Vol 11 (3) ◽  
pp. 365-377
Author(s):  
Negovan Stamenkovic ◽  
Dragana Zivaljevic ◽  
Vidosav Stojanovic
Keyword(s):  
Dynamic Range ◽  
Scaling Function ◽  
Filter Design ◽  
Chinese Remainder Theorem ◽  
Number System ◽  
Residue Number System ◽  
Constant Factor ◽  
Iir Filters ◽  
Reduction Techniques ◽  
Dynamic Range Reduction

Implementation of IIR filters in residue number system (RNS) architecture is more complex in comparison to FIR filters, due to introduction of the scaling function. This function performs operation of division by a constant factor, which is usually the power of two, and after that the operation of rounding. In that way dynamic range reduction in digital systems is achieved. There are different methods for scaling operation implementation, already presented in references. In this paper, some RNS dynamic reduction techniques have been analyzed and then application of one selected technique has been presented on example. In all RNS calculations the power of two moduli set {2n-1, 2n, 2n+1} has been applied.

NOVEL DESIGN AND FPGA IMPLEMENTATION OF DA-RNS FIR FILTERS

2004 ◽  
Vol 13 (06) ◽  
pp. 1233-1249 ◽  
Author(s):  
WEI WANG ◽  
M. N. S. SWAMY ◽  
M. O. AHMAD
Keyword(s):  
Power Efficiency ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Chinese Remainder Theorem ◽  
Low Cost ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Fpga Implementation ◽  
Fir Filters

Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).

LARGE DYNAMIC RANGE RNS SYSTEMS AND THEIR RESIDUE TO BINARY CONVERTERS

2007 ◽  
Vol 16 (02) ◽  
pp. 267-286 ◽  
Author(s):  
ALEXANDER SKAVANTZOS ◽  
MOHAMMAD ABDALLAH ◽  
THANOS STOURAITIS
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Chinese Remainder Theorem ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
New Class ◽  
Mixed Radix Conversion ◽  
Residue Number ◽  
Signal Processors

The Residue Number System (RNS) is an integer system appropriate for implementing fast digital signal processors. It can be used for supporting high-speed arithmetic by operating in parallel channels without need for exchanging information among the channels. In this paper, two novel RNS are proposed. First, a new RNS system based on the modulus set {2n+1, 2n - 1, 2n + 1, 2n + 2(n+1)/2 + 1, 2n - 2(n+1)/2 + 1}, n odd, is developed, along with an efficient implementation of its residue-to-weighted converter. The new RNS is a balanced five-modulus system, appropriate for large dynamic ranges. The proposed residue-to-binary converter is fast and hardware efficient and is based on a one's complement multi-operand adder that adds operands of size only 80% of the size dictated by the system's dynamic range. Second, a new class of multi-modulus RNS systems is proposed. These systems are based on sets consisting of two groups of moduli with the modulus product within one group being of the form 2a(2b - 1), while the modulus product within the other group is of the form 2c - 1. Their RNS-to-weighted converters are based on efficient combinations of the Chinese Remainder Theorem and Mixed Radix Conversion decoding techniques. Systems based on four, five, and seven moduli are constructed and analyzed. The new systems allow efficient implementations for their RNS-to-weighted decoders, imply fast and balanced RNS arithmetic, and may achieve large dynamic ranges. The presented residue-to-weighted converters for these systems rely on simple mod (2x - 1) hardware, which can be easily implemented as one's complement hardware.

scholarly journals Computationally Efficient Approach to Implementation of the Chinese Remainder Theorem Algorithm in Minimally Redundant Residue Number System

2021 ◽  
Author(s):  
Mikhail Selianinau
Keyword(s):  
Chinese Remainder Theorem ◽  
Number System ◽  
Residue Number System ◽  
Computer Applications ◽  
Efficient Approach ◽  
Residue Modulo ◽  
Modern Computer ◽  
New Variant ◽  
Residue Number ◽  
Residue Code

AbstractIn this paper, we deal with the critical problem of performing non-modular operations in the Residue Number System (RNS). The Chinese Remainder Theorem (CRT) is widely used in many modern computer applications. Throughout the article, an efficient approach for implementing the CRT algorithm is described. The structure of the rank of an RNS number, a principal positional characteristic of the residue code, is investigated. It is shown that the rank of a number can be represented by a sum of an inexact rank and a two-valued correction to it. We propose a new variant of minimally redundant RNS, which provides low computational complexity for the rank calculation, and its effectiveness analyzed concerning conventional non-redundant RNS. Owing to the extension of the residue code, by adding the excess residue modulo 2, the complexity of the rank calculation goes down from $O\left (k^{2}\right )$ O k 2 to $O\left (k\right )$ O k with respect to required modular addition operations and lookup tables, where k equals the number of non-redundant RNS moduli.

scholarly journals Improved Modular Division Implementation with the Akushsky Core Function

Computation ◽  
2022 ◽  
Vol 10 (1) ◽  
pp. 9
Author(s):  
Mikhail Babenko ◽  
Andrei Tchernykh ◽  
Viktor Kuchukov
Keyword(s):  
Approximate Method ◽  
Chinese Remainder Theorem ◽  
Number System ◽  
Residue Number System ◽  
Division Algorithm ◽  
Incorrect Result ◽  
Core Function ◽  
Residue Number ◽  
Division Operation

The residue number system (RNS) is widely used in different areas due to the efficiency of modular addition and multiplication operations. However, non-modular operations, such as sign and division operations, are computationally complex. A fractional representation based on the Chinese remainder theorem is widely used. In some cases, this method gives an incorrect result associated with round-off calculation errors. In this paper, we optimize the division operation in RNS using the Akushsky core function without critical cores. We show that the proposed method reduces the size of the operands by half and does not require additional restrictions on the divisor as in the division algorithm in RNS based on the approximate method.

Perspective and Opportunities of Modulo 2n−1 Multipliers in Residue Number System: A Review

2020 ◽  
Vol 29 (11) ◽  
pp. 2030008
Author(s):  
Raj Kumar ◽  
Ritesh Kumar Jaiswal ◽  
Ram Awadh Mishra
Keyword(s):  
Word Length ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
System A ◽  
Essential Components ◽  
Residue Number ◽  
Speed Up ◽  
Computational Circuits

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.

A MEMORYLESS REVERSE CONVERTER FOR THE 4-MODULI SUPERSET {2n - 1, 2n, 2n + 1, 2n + 1 - 1}

2000 ◽  
Vol 10 (01n02) ◽  
pp. 85-99 ◽  
Author(s):  
A. P VINOD ◽  
A. BENJAMIN PREMKUMAR
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Main Challenge ◽  
Reverse Converter ◽  
Residue Number ◽  
Compensation Technique ◽  
The Common ◽  
Performance Computing

This paper presents a residue number system to binary converter in the four moduli set {2n - 1, 2n, 2n + 1, 2n + 1 - 1}, valid for even values of n. This moduli set is an extension of the popular set {2n - 1, 2n + 1}. The number theoretic properties of the moduli set of the form 2n ± 1 are exploited to design the converter. The main challenge of dealing with fractions in Residue Number System is overcome by using the fraction compensation technique. A hardware implementation using only adders is also proposed. When compared to the common three moduli reverse converters, this four moduli converter offers a larger dynamic range and higher parallelism, which makes it useful for high performance computing.

scholarly journals Zero-Aware Low-Precision RNS Scaling Scheme

Axioms ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 5
Author(s):  
Amir Sabbagh Molahosseini
Keyword(s):  
High Precision ◽  
Deep Neural Networks ◽  
State Of The Art ◽  
Chinese Remainder Theorem ◽  
Number System ◽  
Residue Number System ◽  
Scaling Factor ◽  
Improve Performance ◽  
High Area ◽  
Residue Number

Scaling is one of the complex operations in the Residue Number System (RNS). This operation is necessary for RNS-based implementations of deep neural networks (DNNs) to prevent overflow. However, the state-of-the-art RNS scalers for special moduli sets consider the 2k modulo as the scaling factor, which results in a high-precision output with a high area and delay. Therefore, low-precision scaling based on multi-moduli scaling factors should be used to improve performance. However, low-precision scaling for numbers less than the scale factor results in zero output, which makes the subsequent operation result faulty. This paper first presents the formulation and hardware architecture of low-precision RNS scaling for four-moduli sets using new Chinese remainder theorem 2 (New CRT-II) based on a two-moduli scaling factor. Next, the low-precision scaler circuits are reused to achieve a high-precision scaler with the minimum overhead. Therefore, the proposed scaler can detect the zero output after low-precision scaling and then transform low-precision scaled residues to high precision to prevent zero output when the input number is not zero.

Improved Lempel-Ziv-Welch’s Error Detection and Correction Scheme using Redundant Residue Number System (RRNS)

2017 ◽  
Vol 2 (6) ◽  
pp. 25-30 ◽  
Author(s):  
Alhassan Abdul- Barik ◽  
Mohammed Ibrahim Daabo ◽  
Stephen Akobre
Keyword(s):  
Error Detection ◽  
Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Compression Scheme ◽  
Encrypted Data ◽  
Correction Scheme ◽  
Error Detection And Correction ◽  
Residue Number ◽  
Redundant Residue Number System

The greatest difficulty of compressing data is the assurance of the security, integrity, and accuracy of the data in storage in volatile media or transmission in network communication channels. Various methods have been proposed for dealing with the accuracy and consistency of compressed and encrypted data using error detection and correction mechanisms. The Redundant Residue Number System (RRNS) which is a trait of Residue Number System (RNS) is one of the available methods for detecting and correcting errors which involves the addition of extra moduli called redundant moduli. In this paper, Residue Number System (RNS) is efficiently applied to the Lempel-Ziv-Welch (LZW) compression algorithm resulting in new LZW-RNS compression scheme using the traditional moduli set, and two redundant moduli added resulting in the moduli set {2^n-1,〖 2〗^n,〖 2〗^n+1,〖 2〗^2n-3,〖 2〗^2n+1} for the purposes of error detection and correction. This is done by constraining the data or information within the legitimate range of the dynamic range provided by the non-redundant moduli. Simulation with MatLab shows the efficiency and fault tolerance of the proposed scheme than the traditional LZW compression method and other related known state of the art schemes.

scholarly journals Binary to RNS encoder for the moduli set {2n-1, 2n, 2n+1} with embedded diminished-1 channel for DSP application

2016 ◽  
Vol 29 (1) ◽  
pp. 101-112
Author(s):  
Ivan Krstic ◽  
Negovan Stamenkovic ◽  
Vidosav Stojanovic
Keyword(s):  
Dynamic Range ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
The Other ◽  
Minimal Amount ◽  
Residue Number ◽  
Fpga Chip ◽  
The One ◽  
Xilinx Fpga

A binary-to-residues encoder (forward encoder) is an essential building block for the residue number system digital signal processing (RNS DSP) and as such it should be built with a minimal amount of hardware and be efficient in terms of speed and power. The main parts of the forward encoder are residue generators which are usually classified into two categories: the one based on arbitrary moduli-set which make use of look-up tables, and the other based on the special moduli sets. A new memory less architecture of binary-to-RNS encoder based on the special moduli set {2n?1,2n,2n+1} with embedded modulo 2n+1 channel in the diminished-1 representation is presented. Any of two channels (standard modulo 2n +1, or modulo 2n+1 in the diminished-1 representation) operation can be performed by using a single switch. The proposed encoder has been implemented on a Xilinx FPGA chip for the various dynamic range requirements.

scholarly journals Data Hiding in Digital Image for Efficient Information Safety Based on Residue Number System

2021 ◽  
pp. 35-44
Author(s):  
Joseph B. Eseyin ◽  
Kazeem A. Gbolagade
Keyword(s):  
Digital Image ◽  
Chinese Remainder Theorem ◽  
Data Communication ◽  
Number System ◽  
Residue Number System ◽  
Least Significant Bit ◽  
Residue Number ◽  
Information Safety ◽  
Execution Speed ◽  
Almost All

The mass dispersal of digital communication requires the special measures of safety. The need for safe communication is greater than ever before, with computer networks now managing almost all of our business and personal affairs. Information security has become a major concern in our digital lives. The creation of new transmission technologies forces a specific protection mechanisms strategy particularly in data communication state.  We proposed a steganography method in this paper, which reads the message, converting it into its Residue Number System equivalent using the Chinese Remainder Theorem (CRT), encrypting it using the Rivest Shamir Adleman (RSA) algorithm before embedding it in a digital image using the Least Significant Bit algorithm of steganography and then transmitting it through to the appropriate destination and from which the information required to reconstruct the original message is extracted. These techniques will enhance the ability to hide data and the hiding of ciphers in steganographic image and the implementation of CRT will make the device more efficient and stronger. It reduces complexity problems and improved execution speed and reduced the time taken for processing the encryption and embedding competencies.

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