In today's microelectronic packaging, components are continuously designed smaller and assembled more densely to allow more functions to fit into compact portable devices. To enable this trend, more manufacturers are using flip chips that have more I/O's and smaller bumps sizes. This has introduced underfill dispensing that fills the gap between the flip chip and the substrate with polymer epoxy to help reduce thermal and mechanical stress at the bonding interface. In device packaging, the demands for cost reduction and miniaturization encourage the use of wafer-level packaging, such as the chip-on-wafer process. As a result, the challenges to this process have grown exponentially, and so have the challenges to underfill dispensing. For example, to package a device with a chip-last process, the keep-out-zone (KOZ) for underfill epoxy placement to nearby components is shrinking, e.g. from 700um to 300–500um within one year. A high-precision, high-throughput underfill dispensing process has been developed to conquer these challenges. This underfill process is being used in production for chip-on-wafer packaging. In one example, underfill must be dispensed within KOZ 300–500um at UPH 4000. New equipment and new dispensing techniques are under development to further push the limit on higher throughput and precision. Key words: underfill, dispense, microelectronic packaging, device packaging, wafer-level packaging, chip-on-wafer, chip-last, keep-out-zone, precision, throughput
Utilizing an Adaptive Grey Model for Short-Term Time Series Forecasting: A Case Study of Wafer-Level Packaging
