Precise underfill dispense in high-throughput chip-on-wafer packaging

In today's microelectronic packaging, components are continuously designed smaller and assembled more densely to allow more functions to fit into compact portable devices. To enable this trend, more manufacturers are using flip chips that have more I/O's and smaller bumps sizes. This has introduced underfill dispensing that fills the gap between the flip chip and the substrate with polymer epoxy to help reduce thermal and mechanical stress at the bonding interface. In device packaging, the demands for cost reduction and miniaturization encourage the use of wafer-level packaging, such as the chip-on-wafer process. As a result, the challenges to this process have grown exponentially, and so have the challenges to underfill dispensing. For example, to package a device with a chip-last process, the keep-out-zone (KOZ) for underfill epoxy placement to nearby components is shrinking, e.g. from 700um to 300–500um within one year. A high-precision, high-throughput underfill dispensing process has been developed to conquer these challenges. This underfill process is being used in production for chip-on-wafer packaging. In one example, underfill must be dispensed within KOZ 300–500um at UPH 4000. New equipment and new dispensing techniques are under development to further push the limit on higher throughput and precision. Key words: underfill, dispense, microelectronic packaging, device packaging, wafer-level packaging, chip-on-wafer, chip-last, keep-out-zone, precision, throughput

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Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

10.1115/imece2000-2248 ◽

2000 ◽

Author(s):

Y. T. Lin ◽

P. J. Tang ◽

K. N. Chiang

Keyword(s):

Reliability Analysis ◽

Flip Chip ◽

Parametric Design ◽

Material Selection ◽

New Technology ◽

Rapid Expansion ◽

Wafer Level ◽

Good Reliability ◽

Wafer Level Packaging ◽

Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

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A numerical study on mitigation of flying dies in compression molding of microelectronic packages

International Symposium on Microelectronics ◽

10.4071/2380-4505-2018.1.000355 ◽

2018 ◽

Vol 2018 (1) ◽

pp. 000355-000360

Author(s):

Marc Dreissigacker ◽

Ole Hoelck ◽

Joerg Bauer ◽

Tanja Braun ◽

Karl-Friedrich Becker ◽

...

Keyword(s):

Numerical Study ◽

Compression Molding ◽

Packaging Material ◽

Process Conditions ◽

Microelectronic Packaging ◽

Wafer Level ◽

Temperature Dependent ◽

Wafer Level Packaging ◽

Compression Speed ◽

Complex Manner

Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dies during encapsulation in Fan-Out Wafer Level Packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemo-rheology, as well as to extract forces exerted on individual dies. It offers separate evaluation of pressure and shear-contributions for two cases, 0 ° and 45 ° between the dies' frontal area and the melt front. Process parameters, such as compression speed and process temperature, are determined to minimize flying dies and thereby maximize yield. The approach is easily scalable and is therefore well suited to face the challenges that come with the current efforts towards the transition from FOWLP to FOPLP (Fan-Out Panel Level Packaging).

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Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2017dpc-ta2_presentation3 ◽

2017 ◽

Vol 2017 (DPC) ◽

pp. 1-37 ◽

Cited By ~ 1

Author(s):

Amy Lujan

Keyword(s):

Flip Chip ◽

Cost Effective ◽

Cost Comparison ◽

Cost Modeling ◽

Wafer Level ◽

Design Features ◽

Wafer Level Packaging ◽

Flip Chip Packaging ◽

The Right ◽

The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

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Managing Voids in Underfill Process with 5-micron Gap Under Large Die

International Symposium on Microelectronics ◽

10.4071/isom-2012-tp36 ◽

2012 ◽

Vol 2012 (1) ◽

pp. 000376-000383

Author(s):

Hanzhuang Liang ◽

Nordson Asymtek

Keyword(s):

Flip Chip ◽

Substrate Surface ◽

Microelectronic Packaging ◽

Flip Chips ◽

Indium Bumps ◽

Packaging Industry ◽

Complex Features ◽

Capillary Fluid ◽

Near Future ◽

Careful Design

Microelectronic packaging is continuously becoming smaller and denser, thus allowing for more functionalities and smaller devices including portable products. Flip-chip among other technologies continues to enable such trends. In fact denser arrays such as copper pillars or micro bumps of various metallurgies seem to be the technology of choice for the near future electronic interconnect. A technique is reviewed for successfully underfilling a 3cm2 Indium Phosphide flip-chip die mounted on a silicon substrate with 5 microns gap and large number of I/O (about 0.3 million indium bumps) connected in daisy chains. The method that resulted in a void-free underfill consisted of line dispensing along one side of the die such that the flow of the capillary fluid was normal to the direction of the daisy chains. For dot-dispense, substrate surface treatment and more careful design of dispense sequence helped to reduce voids. This study was compared to a manual dot-dispense technique that was unable to meet production throughput requirement, accuracy, repeatability and void-free. Achievement of void-free automated underfill into a 5-micron gap with complex features underneath a large flip chips will encourage today's microelectronic packaging industry to meet the challenges of smaller and denser components.

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On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging

International Symposium on Microelectronics ◽

10.4071/isom-2010-tp5-paper1 ◽

2010 ◽

Vol 2010 (1) ◽

pp. 000325-000332 ◽

Cited By ~ 1

Author(s):

Alan Huffman ◽

Philip Garrou

Keyword(s):

Technological Change ◽

Flip Chip ◽

Emerging Technologies ◽

Unit Area ◽

Form Factors ◽

Electrical Performance ◽

Wafer Level ◽

3D Integration ◽

Wafer Level Packaging ◽

Area Array

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..

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A New Wafer Level Packaging Approach: Encapsulation, Metallization and Laser Structuring for Advanced System in Package Manufacturing

Journal of Electronic Packaging ◽

10.1115/1.1846058 ◽

2005 ◽

Vol 127 (1) ◽

pp. 1-6 ◽

Cited By ~ 7

Author(s):

K.-F. Becker ◽

T. Braun ◽

A. Neumann ◽

A. Ostmann ◽

E. Coko ◽

...

Keyword(s):

System Design ◽

Process Development ◽

Functional System ◽

Single Chip ◽

Wafer Level ◽

Microelectronics Packaging ◽

Flip Chips ◽

Wafer Level Packaging ◽

Electroless Process ◽

Lead Free Solders

One of the general trends in microelectronics packaging is the constant miniaturization of devices. This has led to the development of maximum miniaturization of components on Si level, i.e., CSPs and Flip Chips. To further integrate more functionality into devices, and to further increase the degree of miniaturization, packaging development focus is switching from single chip packaging to the realization of systems in package, SiPs. Two main approaches do exist to realize this goal: one is to integrate all components into one dedicated package, yielding maximum miniaturization for a special application, but little flexibility as far as system design is concerned. The other is to create modular stackable components that can be assembled into a functional system. This integrates both flexibility in system design by exchangeable components and increased reliability potential, as single components can be tested separately. This last approach was considered a promising choice for the generation of SiPs. Within this paper a packaging process is introduced that allows the wafer level manufacturing of stackable, encapsulated devices. Using a transfer molded epoxy demonstrator, a proof-of-concept is performed showing the feasibility of the stackable package approach. This is achieved by combining wafer level encapsulation and molded interconnect device technology. An electroless process for metallization and laser techniques for structuring the metallization layer have been applied to generate structures for reliable interconnects capable for the use of lead-free solders. Summarized, this paper presents the process development and feasibility analysis of wafer level packaging technologies for modular SiP solutions based on a duromer MID approach.

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Design and Fabrication of WLP Compatible Miniaturized Pressure Sensor System with Through Silicon Via (TSV) Interconnects

International Symposium on Microelectronics ◽

10.4071/isom-2011-ta1-paper5 ◽

2011 ◽

Vol 2011 (1) ◽

pp. 000033-000043 ◽

Cited By ~ 1

Author(s):

Tao WANG ◽

Jian CAI ◽

Qian WANG ◽

Hao ZHANG ◽

Zheyao WANG

Keyword(s):

Pressure Sensor ◽

Flip Chip ◽

Electrical Signal ◽

Sensor System ◽

Wafer Level ◽

Through Silicon Via ◽

Bonding Structure ◽

Wafer Level Packaging ◽

Piezoresistive Pressure Sensor ◽

Processing Circuit

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically. The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.

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Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

International Symposium on Microelectronics ◽

10.4071/isom-2011-tha3-paper1 ◽

2011 ◽

Vol 2011 (1) ◽

pp. 000953-000960 ◽

Cited By ~ 3

Author(s):

Thomas Oppert ◽

Rainer Dohle ◽

Jörg Franke ◽

Stefan Härter

Keyword(s):

Solder Ball ◽

Flip Chip ◽

Temperature Cycling ◽

Solder Paste ◽

Wafer Level ◽

Solder Alloys ◽

Flip Chips ◽

Fine Pitch ◽

Solder Bumps ◽

Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

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