A Self-Repairing Digital System with High-Quality Scalability and Fault Coverage

2018 ◽  
Vol 6 (8) ◽  
pp. 235
Author(s):  
S. Ravichand ◽  
T. Madhu ◽  
M. Sailaja
Keyword(s):  
Genetic Algorithm ◽  
Circuit Design ◽  
Fault Tolerant ◽  
Current System ◽  
Satellite Broadcasting ◽  
Area Overhead ◽  
Free Block ◽  
Utmost Care ◽  
Logical Errors ◽  
Active Block

In any fault tolerant or BIST system the primary goal is to covenant with faults that arise in the indented system. The proposed system using genetic algorithm to optimize the performance and area of given circuit.  This approach is supple for combinational circuit design. The use of four spare cells simplifies the operation of the active block in the current system; it needs more space to establish itself so it is considered as overhead. The proposed method of fault detection and correction for logical errors using genetic algorithm decreases the area overhead. Detection of Fault in the memory unit through BIST implementation increases the speed but replacing the existing faulty block with fault free block degrades the fault analyzing capabilities. Utmost care has on all the works implemented for the process of minimizing the error in different digital process. Therefore, with the new scope of proposing the method of reducing the error flow for the application of medical field, aeronautical, satellite broadcasting is described very efficiently in this paper. The simulation results of the fault tolerant and self-repairing method using genetic algorithm is presented.

3A Fault Tolerant Low Side Driver Circuit Design Using Design FMEA for Automotive Applications

2019 ◽  
Author(s):  
Sri Navaneeth Easwaran ◽  
Martin Mollat ◽  
Deepak Sreedharan ◽  
Samir Camdzic ◽  
Sunil Venugopal Kashvap ◽  
...  
Keyword(s):  
Circuit Design ◽  
Fault Tolerant ◽  
Automotive Applications ◽  
Driver Circuit

scholarly journals Fault Tolerant PLBGSA: Precedence Level Based Genetic Scheduling Algorithm for P2P Grid

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Piyush Chauhan ◽  
Nitin
Keyword(s):  
Genetic Algorithm ◽  
Directed Acyclic Graph ◽  
Fault Tolerant ◽  
Scheduling Algorithm ◽  
Complex Task ◽  
Grid Scheduling ◽  
Complex Tasks ◽  
Small Organizations ◽  
Grid Resources ◽  
Desirable Trait

Due to monetary limitation, small organizations cannot afford high end supercomputers to solve highly complex tasks. P2P (peer to peer) grid computing is being used nowadays to break complex task into subtasks in order to solve them on different grid resources. Workflows are used to represent these complex tasks. Finishing such complex task in a P2P grid requires scheduling subtasks of workflow in an optimized manner. Several factors play their part in scheduling decisions. The genetic algorithm is very useful in scheduling DAG (directed acyclic graph) based task. Benefit of a genetic algorithm is that it takes into consideration multiple criteria while scheduling. In this paper, we have proposed a precedence level based genetic algorithm (PLBGSA), which yields schedules for workflows in a decentralized fashion. PLBGSA is compared with existing genetic algorithm based scheduling techniques. Fault tolerance is a desirable trait of a P2P grid scheduling algorithm due to the untrustworthy nature of grid resources. PLBGSA handles faults efficiently.

scholarly journals Speciation-based genetic algorithm in analog circuit design

2016 ◽  
Vol 24 ◽  
pp. 1022-1033
Author(s):  
Hasari KARCİ ◽  
Gülay TOHUMOĞLU ◽  
Arif NACAROĞLU
Keyword(s):  
Genetic Algorithm ◽  
Circuit Design ◽  
Analog Circuit ◽  
Analog Circuit Design

Optimal Bacon-Shor codes

2013 ◽  
Vol 13 (5&6) ◽  
pp. 490-510
Author(s):  
John Napp ◽  
John Preskill
Keyword(s):  
Error Rate ◽  
Upper Bound ◽  
Error Probability ◽  
Fault Tolerant ◽  
Phase Error ◽  
Block Size ◽  
Effective Protection ◽  
Logical Error ◽  
Logical Errors ◽  
Bit Flip

We study the performance of Bacon-Shor codes, quantum subsystem codes which are well suited for applications to fault-tolerant quantum memory because the error syndrome can be extracted by performing two-qubit measurements. Assuming independent noise, we find the optimal block size in terms of the bit-flip error probability $p_X$ and the phase error probability $p_Z$, and determine how the probability of a logical error depends on $p_X$ and $p_Z$. We show that a single Bacon-Shor code block, used by itself without concatenation, can provide very effective protection against logical errors if the noise is highly biased ($p_Z/p_X\gg 1)$ and the physical error rate $p_Z$ is a few percent or below. We also derive an upper bound on the logical error rate for the case where the syndrome data is noisy.

scholarly journals A Fault Tolerant Voter for Approximate Triple Modular Redundancy

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 332 ◽  
Author(s):  
Tooba Arifeen ◽  
Abdus Hassan ◽  
Jeong-A Lee
Keyword(s):  
Fault Tolerant ◽  
Triple Modular Redundancy ◽  
Area Overhead ◽  
Final Output ◽  
Working Principle ◽  
Fault Masking ◽  
Internal Faults ◽  
Modular Redundancy ◽  
Power Delay Product

Approximate Triple Modular Redundancy has been proposed in the literature to overcome the area overhead issue of Triple Modular Redundancy (TMR). The outcome of TMR/Approximate TMR modules serves as the voter input to produce the final output of a system. Because the working principle of Approximate TMR conditionally allows one of the approximate modules to differ from the original circuit, it is critical for Approximate TMR that a voter not only be tolerant toward its internal faults but also toward faults that occur at the voter inputs. Herein, we present a novel compact voter for Approximate TMR using pass transistors and quadded transistor level redundancy to achieve a higher fault masking. The design also targets a better Quality of Circuit (QoC), a new metric which we have proposed for highlighting the ability of a circuit to fully mask all possible internal faults for an input vector. Comparing the fault masking features with those of existing works, the proposed voter delivered upto 45.1%, 62.5%, 26.6% improvement in Fault Masking Ratio (FMR), QoC, and reliability, respectively. With respect to the electrical characteristics, our proposed voter can achieve an improvement of up to 50% and 56% in terms of the transistor count and power delay product, respectively.

scholarly journals A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1076 ◽  
Author(s):  
Zulqar Nain ◽  
Rashid Ali ◽  
Sheraz Anjum ◽  
Muhammad Khalil Afzal ◽  
Sung Won Kim
Keyword(s):  
Fault Tolerant ◽  
Current System ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Traffic Load ◽  
Delivery Ratio ◽  
Processing Elements ◽  
System On A Chip ◽  
On Chip ◽  
Network On A Chip

Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

Vehicle Health Inferencing Using Feature-Based Neural-Symbolic Networks

2013 ◽  
Author(s):  
Christopher M. Aasted ◽  
Sunwook Lim ◽  
Rahmat A. Shoureshi
Keyword(s):  
Historical Data ◽  
Fault Tolerant ◽  
Current System ◽  
Diagnostic Information ◽  
Aerial Vehicles ◽  
Feature Based ◽  
Incident Data ◽  
Autonomous Aerial Vehicles ◽  
Diagnostics System

In order to optimize the use of fault tolerant controllers for unmanned or autonomous aerial vehicles, a health diagnostics system is being developed. To autonomously determine the effect of damage on global vehicle health, a feature-based neural-symbolic network is utilized to infer vehicle health using historical data. Our current system is able to accurately characterize the extent of vehicle damage with 99.2% accuracy when tested on prior incident data. Based on the results of this work, neural-symbolic networks appear to be a useful tool for diagnosis of global vehicle health based on features of subsystem diagnostic information.

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